[A] Suppose that a 16M x 32 main memory is built using 512K x 16 RAM chips and that the memory is word addressable. a- How many RAM chips are necessary to build the 16M x 32 main memory? b- If we were accessing one full work, how many chips would be involved? C- How many address bits are need for each RAM chip? d- How may memory banks will this memory have? How many address bits are needed for all memory? е-

[A] Suppose that a 16M x 32 main memory is built using 512K x 16 RAM chips and that the memory is word addressable. a- How many RAM chips are necessary to build the 16M x 32 main memory? b- If we were accessing one full work, how many chips would be involved? C- How many address bits are need for each RAM chip? d- How may memory banks will this memory have? How many address bits are needed for all memory? е-

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

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If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the fetch cycle is 40% of the processor cycle time, what memory access speed is required to implement load operations with zero wait states and load operations with two wait states?
Most Intel CPUs use the __________, in which each memory address is represented by two integers.
3. Suppose that a 16M x 16 main memory is built using 512K x 8 RAM chips and that memory is word addressable. a) How many RAM chips are necessary? b) If we were accessing one full word, how many chips would be involved? c) How many address bits are needed for each RAM chip? d) How many banks will this memory have? e) How many address bits are needed for all memory? f) If high-order interleaving is used, where would address 14 (which is E in hex) be located? g) If low-order interleaving is used, where would address 14 (which is E in hex) be located?
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Suppose that a 2M x 16 main memory is built using 256K x 8 RAM chips and that memory is word addressable. a) How many RAM chips are necessary? b) if we were accessing one full word, how many chips would be involved? c) How many address bits are needed for each RAM chips? d) How many banks will this memory have? e) How many address bits are needed for all the memory? f) If high-order interleaving is used,where would address 14 (which is E in hex) be located?
Suppose that a 32M X 32 memory built using 512K X 8 RAM chips and memory is word-addressable. 1) How many RAM chips are necessary? 2) If we were accessing one full word, how many chips would be involved? 3) How many address bits are needed for each RAM chip? 4) How many banks will this memory have? 5f) If high-order interleaving is used, where would address 0x11011 be located? (Answer should be: bank# & offset#)
Suppose that a 2M x 16 main memory is built using 256K × 8 RAM chips and memory is word-addressable. a) How many RAM chips are necessary? b) If we were accessing one full word, how many chips would be involved? c) How many address bits are needed for each RAM chip?
Suppose that a 2M × 16 main memory is built using 256K × 8 RAM chips and that memory is word addressable.1. a) How many RAM chips are necessary?2. b) If we were accessing one full word, how many chips would be involved? 3. c) How many address bits are needed for each RAM chip?4. d) How many banks will this memory have?5. e) How many address bits are needed for all memory?6. f) If high-order interleaving is used, where would address 14 (which is E in hex) be located?7. g) Repeat exercise 9f for low-order interleaving.
Suppose we have 1G x 16 RAM chips that make up a 32G x 64 memory that uses high-order interleaving. (This means that each word is 64 bits in size and there are 32G of these words.) a) How many RAM chips are necessary? b) Assuming four chips per bank, how many banks are required? c) How many lines must go to each chip? d) How many bits are needed for a memory address, assuming it is word addressable? e) For the bits in part d, draw a diagram indicating many and which bits are used for chip select, and how many and which bits are used for the address on the chip.
Assume that we have a computer system with a main memory consists of 4 RAM chips [RAM 0, RAM 1, RAM 2, RAM 3] in which each chip is in one row. Moreover, each RAM chip is word-addressable with 64 bits per word. The size of address bus is 30 bits. What is the size of data bus? How many bits are required to select RAM chips? How many bits are required to select: memory locations? What is the total size of main memory? If the memory uses the following ordering for the address bus: Data location selecting Which interleaving method this memory uses? If we have (000000000000000111010001110101)2 on the address bus, which RAM chip will be selected? RAM selecting
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