Q4/ A- How many: 1- memory locations can be addressed by a microprocessor with 14 address lines? 2- chips are required to make up 1k byte of memory, If the memory chip size is 256 X 1 bits? 3- address line are necessary to address two megabytes (2048k) of memory? 4- bits are stored by a 256 X 4 memory chip? Can this chip be specified as 128 byte memory? 5- lines must be decoded to generate five chip select signals? B- What it is the addressing mode instructions in 8086, list it with examples.
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- If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the fetch cycle is 40% of the processor cycle time, what memory access speed is required to implement load operations with zero wait states and load operations with two wait states?Most Intel CPUs use the __________, in which each memory address is represented by two integers.Suppose that a 2M × 16 main memory is built using 256K × 8 RAM chips and that memory is word addressable.1. a) How many RAM chips are necessary?2. b) If we were accessing one full word, how many chips would be involved? 3. c) How many address bits are needed for each RAM chip?4. d) How many banks will this memory have?5. e) How many address bits are needed for all memory?6. f) If high-order interleaving is used, where would address 14 (which is E in hex) be located?7. g) Repeat exercise 9f for low-order interleaving.
- A microprocessor has a 32-bit address line. The size of the memory contents of each address is 8 bits. The memory space is defined as the collection of memory position the processor can address. What is the address range (lowest to highest, in hexadecimal) of the memory space for this microprocessor? What is the size (in bytes, KB, or MB) of the memory space? 1 KB = 21010 bytes, 1MB = 22020 bytes, 1GB = 23030 bytes A memory device is connected to the microprocessor. Base o the size of the memory, the microprocessor has assigned the addresses 0xA4000000 to 0xA07FFFFF to this memory device. What is the size (in bytes, KB, or MB) of this memory device? What is the minimum number of bits required to represent the addresses only for this memory device?Suppose that a 64M x 16 main memory is built using 512K × 8 RAM chips and memory is word-addressable. a) How many RAM chips are necessary?b) If we were accessing one full word, how many chips would be involved?c) How many address bits are needed for each RAM chip?d) How many banks will this memory have?e) How many address bits are needed for all of memory?f) If high-order interleaving is used, where would address 32(base 10) be located? (Your answer should be "Bank#, Offset#")g) Repeat (f) for low-order interleaving.Suppose that a 16M x 16 main memory is built using 512K x 8 RAM chips and that memory is word addressable. a) How many RAM chips are necessary? b) If we were accessing one full word, how many chips would be involved? c) How many address bits are needed for each RAM chip? d) How many banks will this memory have? e) How many address bits are needed for all memory? f) If high-order interleaving is used, where would address 14 (which is E in hex) be located? g) If low-order interleaving is used, where would address 14 (which is E in hex) be located?
- Suppose we have 1G x 16 RAM chips that make up a 32G x 64 memory that uses high-order interleaving. (This means that each word is 64 bits in size and there are 32G of these words.) a) How many RAM chips are necessary? b) Assuming four chips per bank, how many banks are required? c) How many lines must go to each chip? d) How many bits are needed for a memory address, assuming it is word addressable? e) For the bits in part d, draw a diagram indicating many and which bits are used for chip select, and how many and which bits are used for the address on the chip.Suppose that a 32M X 32 memory built using 512K X 8 RAM chips and memory is word-addressable. 1) How many RAM chips are necessary? 2) If we were accessing one full word, how many chips would be involved? 3) How many address bits are needed for each RAM chip? 4) How many banks will this memory have? 5f) If high-order interleaving is used, where would address 0x11011 be located? (Answer should be: bank# & offset#)Consider the interfacing of a RAM to an 8086 microprocessor as shown in the figure below. If the starting address of the RAM is 00000H. RAM1 = 64K , RAM2 = 64K , RAM3 = 32K , RAM4 = 64K ,and RAM5 = 32K bytes. What is the address of the last location of RAM3?
- Suppose that a 4M × 32 main memory is built using 128K × 8 RAM chips and memory is word addressable (word size = 32 bits)a. How many RAM chips are needed?b. How many chips would be involved when accessing a full word?c. How many banks will this memory have?d. How many address bits are needed for the whole main memory?e. If high-order interleaving is used, where would the address 7060016 be located (in which bank)?f. If low-order interleaving is used, where would the address 2C77D516 be located?Suppose that a 2M x 16 main memory is built using 256K × 8 RAM chips and memory is word-addressable. a) How many RAM chips are necessary? b) If we were accessing one full word, how many chips would be involved? c) How many address bits are needed for each RAM chip?Suppose the RAM for a certain computer has 4M words, where each word is 16 bits long. What is the capacity of this memory expressed in bytes? If this RAM is byte addressable, how many bits must an address contain? If this RAM is word addressable, how many bits must an address contain?