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- A 32-bit computer has a memory of 256 KB and a cache line size of 64 bytes. The memory cache access time is 5ns. This cache is 4-way associative and use LRU as a replacement algorithm. a) What is the number of lines and sets of this memory cache? b) What is the block size transferred between the cache memory and the main memory? c) If the time to transfer a line to cache memory is 200 ns, what is the hit ratio needed to obtain an average access time of 20 ns?Suppose a computer using fully associative cache has 224224 bytes of byte-addressable main memory and a cache of 128 blocks, where each cache block contains 64 bytes. (a) How many blocks of main memory are there? (b) What is the format of a memory address as seen by the cache? (c) To which cache block will the memory address 0xD87216 map?A microprocessor with 32-bit address bus has an on-chip 16-KByte four-way set-associative cache memory, the line size is 4 bytes. Draw a block diagram of this cache showing its Organization and how the different address fields are used to determine a cache hit/miss. Where in the cache is the word from memory location ABCDE8F8 mapped?
- Suppose a byte-addressable computer using set-associative cache has 216 bytes of main memory and a cache of 32 blocks, and each cache block contains 8 bytes.Q.) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?A CPU has 32-bit memory address and a 256 KB cache memory. The cache is organized as a 4-way set associative cache with cache block size of 16 bytes. a. What is the number of sets in the cache? b. What is the size (in bits) of the tag field per cache block? c. What is the number and size of comparators required for tag matching? d. How many address bits are required to find the byte offset within a cache block? e. What is the total amount of extra memory (in bytes) required for the tag bits?The memory access time is 1 nanosecond for a read operation with a hit in cache, 5 nanoseconds for a read operation with a miss in cache, 2 nanoseconds for a write operation with a hit in cache and 10 nanoseconds for a write operation with a miss in cache. Execution of a sequence of instructions involves 100 instruction fetch operations, 60 memory operand read operations and 40 memory operand write operations. The cache hit-ratio is 0.9. The average memory access time (in nanoseconds) in executing the sequence of instructions will be ?
- In a Direct Mapped Cache Memory Physical Address format the Cache line offset field size and word offset field size are same (with word size of one Byte). The number of tag bits in the Physical Address format is equal to the number of blocks in Cache Memory. If the Tag field Size is Mega words. 16 bits, the size of the physical Memory isOne of the major functional characteristics of computer memory is latency. For the latency it is true O a. it does not affect the memory speed O b. it is related to the number of information units (bits) that can be stored O c. it is related to the probability for a miss or a hit in the cache memory O d. it is related to the cache coherency it is related to the number of bits of the bus connecting the memory to the CPU е. O f. it affects the memory speed O g. it helps to distinguish between static and dynamic memory O h. it is not related to the intermediate stage between the CPU and the main memory known as cache memoryOn the Motorola 68020 microprocessor, a cache access takes two clock cycles. Data access from main memory over the bus to the processor takes three clock cycles in the case of no wait state insertion; the data are delivered to the processor in parallel with delivery to the cache. a. Calculate the effective length of a memory cycle given a hit ratio of 0.9 and a clocking rate of 16.67 MHz. b. Repeat the calculations assuming insertion of two wait states of one cycle each per memory cycle. What conclusion can you draw from the results?
- If memory read cycle takes 100 ns and a cache read cycle takes 20 ns, then for four continuous references, the first one brings the main memory contents to cache and the next three from cache. Find the time taken for the Read cycle with and without Cache? What is the Percentage speedup obtained?Suppose a computer using fully associative cache has 224 bytes of byte-addressable main memory and a cache of 128 blocks, where each block contains 64 bytes.Q.) What is the format of a memory address as seen by cache; that is, what are the sizes of the tag and offset fields?Suppose a computer using fully associative cache has 216 bytes of byte-addressable main memory and a cache of 64 blocks, where each cache block contains 32 bytes.Q.) What is the format of a memory address as seen by the cache; that is, what are the sizes of the tag and offset fields?