The following table provides the statistics of a cache for a particular program. The base CPI (without cache misses) is 1, and the memory bus bandwidth (the bandwidth to transfer data between cache and memory) is 4 bytes per bus cycle, and it takes one bus cycle to send the address before data transfer. The memory spends 10 bus cycles to store data from thebus or write data to bus. The clock rate used by memory and the bus is a quarter of the CPU clock rate. Data reads per 1000 instructions = 100 Data writes per 1000 instructions = 150 %3D Instruction cachemiss rate = 0.4% Data cachemiss rate = 3% Block size(bytes) = 32 bytes a) If the cache uses write-through and non-write- allocate, what is the effective CPI? Assume there is a write buffer which is full 10% of the time it is accessed .b) If the cache uses write-back and write-allocate, what is the effective CPI? Assume 20% of replaced data cache blocks are dirty, and there is no write buffer.c) Repeat (a) and (b) assuming both critical-word-first and early- restart are used. c) Repeat (a) and (b) assuming both critical-word-first and early-restart are used.
The following table provides the statistics of a cache for a particular program. The base CPI (without cache misses) is 1, and the memory bus bandwidth (the bandwidth to transfer data between cache and memory) is 4 bytes per bus cycle, and it takes one bus cycle to send the address before data transfer. The memory spends 10 bus cycles to store data from thebus or write data to bus. The clock rate used by memory and the bus is a quarter of the CPU clock rate. Data reads per 1000 instructions = 100 Data writes per 1000 instructions = 150 %3D Instruction cachemiss rate = 0.4% Data cachemiss rate = 3% Block size(bytes) = 32 bytes a) If the cache uses write-through and non-write- allocate, what is the effective CPI? Assume there is a write buffer which is full 10% of the time it is accessed .b) If the cache uses write-back and write-allocate, what is the effective CPI? Assume 20% of replaced data cache blocks are dirty, and there is no write buffer.c) Repeat (a) and (b) assuming both critical-word-first and early- restart are used. c) Repeat (a) and (b) assuming both critical-word-first and early-restart are used.
Chapter4: Processor Technology And Architecture
Section: Chapter Questions
Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...
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Transcribed Image Text:The following table provides the statistics of a cache for
a particular program. The base CPI (without cache
misses) is 1, and the memory bus bandwidth (the
bandwidth to transfer data between cache and memory)
is 4 bytes per bus cycle, and it takes one bus cycle to
send the address before data transfer. The memory
spends 10 bus cycles to store data from thebus or write
data to bus. The clock rate used by memory and the bus
is a quarter of the CPU clock rate.
Data reads per 1000 instructions = 100
Data writes per 1000 instructions = 150
%3D
Instruction cachemiss rate = 0.4%
Data cachemiss rate = 3%
Block size(bytes) = 32 bytes
a) If the cache uses write-through and non-write-
allocate, what is the effective CPI? Assume there is a
write buffer which is full 10% of the time it is accessed
.b) If the cache uses write-back and write-allocate, what
is the effective CPI? Assume 20% of replaced data cache
blocks are dirty, and there is no write buffer.c) Repeat (a)
and (b) assuming both critical-word-first and early-
restart are used.
c) Repeat (a) and (b) assuming both critical-word-first
and early-restart are used.
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