A hierarchical cache-main memory subsystem has the following specifications: (1) Cache access time of 50 nsec (ii) Main memory access time of 500 nsec (iii) 80% of memory request are for read (iv) Hit ratio of 0.9 for read access and the write-through scheme is used. Calculate the following: (a) Average access time of he memory system considering only memory read cycle.

A hierarchical cache-main memory subsystem has the following specifications: (1) Cache access time of 50 nsec (ii) Main memory access time of 500 nsec (iii) 80% of memory request are for read (iv) Hit ratio of 0.9 for read access and the write-through scheme is used. Calculate the following: (a) Average access time of he memory system considering only memory read cycle.

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

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If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the fetch cycle is 40% of the processor cycle time, what memory access speed is required to implement load operations with zero wait states and load operations with two wait states?
A hierarchical cache-main memory subsystem has the following specificatioNs: (i) Cache access time of 50 nsec (ii) Main memory access time of 500 nsec (iii) 80% of memory request are for read (iv) Hit ratio of 0.9 for read access and the write-through scheme is used. Calculate the following: (a) Average access time of he memory system considering only memory read cycle. (b) Average access time of the system both for read and write requests.
A 32-bit computer has a memory of 256 KB and a cache line size of 64 bytes. The memory cache access time is 5ns. This cache is 4-way associative and use LRU as a replacement algorithm. a) What is the number of lines and sets of this memory cache? b) What is the block size transferred between the cache memory and the main memory? c) If the time to transfer a line to cache memory is 200 ns, what is the hit ratio needed to obtain an average access time of 20 ns?
Question 7: A computer system has a main memory of 64 Mbytes, 256 Kbytes cache memory and two-way set associative mapping with block size of 16 bytes. Assume that a computer uses a byte-addressable mechanism. Determine: a) Main memory address structure. b) Number of blocks in the main memory. c) Number of lines in each cache memory set.
Question (la) A cache system is to be designed to store data from a 256 MB memory space. If each block of main memory contains 16 words, determine the number of blocks that are needed and draw the logical organization of the full address identifying the block ID portion and the word (offset) portion. The IEEE Standard 754 representation of a floating-point number is given as: 01011011001100110101000000000000 base on your knowledge on floating point numbers determine the binary value represented by this number. a real-world object, processes A digital weighing scale measures the weight the data and stores it in binary form. Using the principles of digital signal processing, practically explain how this phenomenon occurs.
Assume that a system is using write-though cache. It has 70% write hits. The cache operates in look-aside mode with a read-hit ratio of 80%. The program run on the system is such that it has memory reference for read 70% of time and for write is 30%. The main memory cycle time is 100ns and the cache access is 20ns.(Further assume we are using no write allocate policy) Difference between average write access time and average read access time is (in ns).
A cache system is to be designed to store data from a 256 MB memory space. If each block of main memory contains 16 words, determine the number of blocks that are needed and draw the logical organization of the full address identifying the block ID portion and the word (offset) portion
Suppose a byte-addressable computer using set associative cache has 224 bytes of main memory and a cache size of 64K bytes, and each cache block contains 32 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?
Suppose a byte-addressable computer using set associative cache has 216 bytes of main memory and a cache of 32 blocks, and each cache block contains 8 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?
5. Suppose a byte-addressable computer using set-associate cache has 2^21 bytes of main memory and a cache of 64 blocks, where each cache block contains 16 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache; that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache; that is, what are the sizes of the tag, set, and offset fields?
2. Consider a computer with the following characteristics: total of 1Mbyte of main memory; Content of each addressable location is 1 byte; block size of 16 bytes; and cache size of 64 Kbytes. (a) For the main memory addresses of F0010, 01234, and CABBE, give the corresponding tag, cache line address, and word offsets for a direct-mapped cache. (b) Give any two main memory addresses with different tags that map to the same cache slot for a direct-mapped cache. (c) For the main memory addresses of F0010 and CABBE, give the corresponding tag and offset values for a fully-associative cache. (d) For the main memory addresses of F0010 and CABBE, give the corresponding tag, cache set, and offset values for a two-way set-associative cache.
A cache memory needs an access time of 30 ns and main memory 150 ns, what is the average access time of CPU (assume hit ratio= = 80%)?