A memory system consists of a cache and a main memory. It takes 25ns to access the cache, and 100ns to access the main memory. If the effective memory access time is 40% greater that the cache access time, what is the miss ratio MR? Express the MR as a percentage i.e. as an integer between 0 and 100. (Drop decimal digits, if any.)
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- Exercise 2: A byte addressable memory has a size of 1024 MBytes. This memory is attached to a direct mapping cache of 32KBytes that contains 1024 lines. a. What is the memory address length? b. What is the block size? c. What is the number of blocks in main memory? d. What is the length in bit of: tag (T), line number (L) and byte number (W)? e. Determine in Hexadecimal the tag (T), line number (L) and byte number (W) of the following Hexadecimal memory address: 000008AE f. What is the block that contains the address 000000DE? g. Which line of the cache can hold the block containing 000000DE?Assume the following values are stored at the indicated memory addresses and registers Address Value 0x100 0xaaa 0x104 0x123 0x108 0x12 0x10c 0x10 Register Value %eax 0x100 %ecx 0x1 %edx 0x3 Fill up the following table: %eax 0x104 $0x108 (%eax) 4(%eax) 9(%eax,%edx) 260(%ecx,%edx) 0xFC(,%ecx,4) (%eax,%edx,4)Assume the following distribution of instructions for a given program: Arithmetic Store Load Branch Number of instructions CPI operations 680 2 operations operations operations 40 1 120 160 5 4 4.1. What are the execution time and the average CPI of the above program on a 2.0 GHz processor? 4.2. If the number of store instructions can be reduced by half and the number of load operations can be reduced by 25%, then what is the total speed-up in program execution time and the new average CPI of the above program executed on 3.0 GHz processor?
- Assume the memory contains 6 holes with the sizes of 190, 550, 220, 420, 650, and 110 A sequence of requests for 4 blocks is to be satisifed: A = 210, B = 430, C = 100, D = 420. The following table has two rows for each of the four memory allocation strategies (first fit, next fit, best fit, worst fit). Fill in the table as follows: Block Allocated: Enter the letter of the memory block that will be placed in the indicated hole. If more than one block is allocated in a hole, include both blocks with no spaces (e.g. "DG"). If no block is allocated in a hile, enter "-". • Remaining Size: Enter the size of the remaining hole after all four memory blocks are placed. H1: 190 H2: 550 H3: 220 H4: 420 H5: 650 H6: 110 Block First Fit Blank 1 Blank 2 Blank 3 Blank 4 Blank 5 Blank 6 Allocated Remaining Blank 7 Blank 8 Blank 9 Blank 10 Blank 11 Blank 12 Size Block Next Fit Blank 13 Blank 14 Blank 15 Blank 16 Blank 17 Blank 18 Allocated Remaining Blank 19 Blank 20 Blank 21 Blank 22 Blank 23 Blank 24…If random access memory (RAM) and cache memory (both of which are comprised of transistors), then what is the function of cache memory? Do we need several different forms of memory, or can we get by with only one?8) The physical address is the actual location within the RAM. It is put on the address bus by the CPU to be decoded by the memory circuitry. If CS = 426FH and IP A436 H, determine the following: %3D a) Logical address, b) Offset address, c) Physical address, d) Lower range of the code segnment, and e) Upper range of the code segment.
- By assuming that X is the last digit of your student number and 3X is a two digitnumber, consider memory storage of a 64-bit word stored at memory word 3X ina byte-addressable memory(a) What is the byte address of memory word 3X?(b) What are the byte addresses that memory word 3X spans?(c) Draw the number 0xF1234567890ABCDE stored at word 3X in both big-endianand little-endian machines. Clearly label the byte address corresponding to eachdata byte value.5. A computer of 32 bits has a cache memory of 64 KB with a cache line size of 64 bytes. The cache access time is 20 ns, and the miss penalty is 120 ns. The cache is 2-way associative. a) What is the number of cache lines? b) What is the number of cache sets? c) What is the number of lines per set? d) Draw a scheme of this cache. e) Calculate the time to read a word in case of miss.Q3\if o001= Load AC from memory, 0010 = Store AC to memory, 0101= Add to AC from memory Where we have three memory location 500,501 and 502 the contents in first location is 1880, the contents in second location is 5881 and the contents in third location is 2881. the contents of 880 is 0002 and the contents of 881 is 0003 .DRAW a diagram that show the contents of PC,IR and AC at the end of program ?
- the available space list of a computer memory is specified as follows: 9 start address block address in words 100 50 200 150 450 600 1200 400 determine the available space list after allocating the space for the stream of requests consisting of the following block sizes: 25,100,250,200,100,150 use i) first fit ii) best fit and iii) worst fit algorithmsQuestion 2 You are running a program that performs a data summation operation with a supercomputer with 32768 computing nodes (i.e., processing unit: CPU). Assume that the data has 100,000 numbers, measure (1) total running time, (2) speedup, and (3) efficiency. You can calculate the approximated time (not exact time). Please note that there are several assumptions as Computation - Each PE can add two numbers stored in its local memory in one second. Communication - A PE can send data from its local memory to the local memory of any other PE in three seconds (independent of the size of the data). Each PE can send data elements from one PE to another. Input and output - At the beginning of the program, the whole input array A is stored in PE #0. In the end, the result should be gathered in PE #0. Synchronization - All PEs operate in a lock-step manner; i.e., they can either compute, communicate, or be idle. Use the editor to format your answerMemory Address Memory Content Øx20000013 Øx79 Øx20000012 Өхcd Øx20000011 Øxa3 Øx20000010 Oxfd ØX2000000F Øx12 According to the memory view given below, if RO = 0x20000004, after executing the LDMIA r0, {r7, r3, r9} instruction, which of the following are the contents of the r3 and r0 registers, respectively (data layout big endian)? Øx2000000E Øxod ØX2000000D Øxe0 Øx2000000C Өxeb ØX2000000B Øx2c ØX2000000A Øx1a Øx20000009 Øxdc Øx20000008 Ox11 Øx20000007 Өx34 Øx20000006 Øxce Øx20000005 Øxfd Øx20000004 Øxe4 Øx20000003 Øxa2 Øx20000002 Øx3f Øx20000001 Øx06 Øx20000000 Øxf5 Lütfen birini seçin: O A. R3= 0X2C1ADC11 ro =0x20000010 O B. R3= 0X34CEFDE4 r0 =0x20000010 O C. R3= 0X11DC1A2C ro =0x2000000C O D. R3= 0XE4FDCE34 ro =0x20000010 O E. R3= 0XE4FDCE34 ro =0x20000004