If a processor has a CPI of 2 without any memory stalls, and the miss penalty is 100 cycles for all misses, determine how much faster a processor would run with a perfect cache that never missed in the following two scenarios. Assume the frequency of all loads and stores is 30%. a) Miss rate of an instruction cache is 2% and the miss rate of data cache is 5% b) Miss rate of an instruction cache is 1% and the miss rate of data cache is 2%.

If a processor has a CPI of 2 without any memory stalls, and the miss penalty is 100 cycles for all misses, determine how much faster a processor would run with a perfect cache that never missed in the following two scenarios. Assume the frequency of all loads and stores is 30%. a) Miss rate of an instruction cache is 2% and the miss rate of data cache is 5% b) Miss rate of an instruction cache is 1% and the miss rate of data cache is 2%.

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

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A program sees a 4% miss rate on both the Instruction Cache and the Data Cache. Every instruction requires access to the Instruction cache. Only 35% of the instructions require data access from the Data Cache. The miss penalty for either the data or the instruction cache is 100 cycles. Assume the average Clocks per Instruction (CPI) is 2 without any memory stalls (this is a hypothetical machine where if there were no misses on that instruction, it would get executed in 2 clock cycles. We are not worrying about how it is implemented, just, that suppose it was possible). Assume the number of instructions in a program is X. F1: What is the number of 'instruction miss cycles'? (The number of clock cycles lost due to a miss on the Instruction Cache) F2: What is the number of 'data miss cycles'? F3: What is the total run time of the program including the missed cycles dues to data and instruction misses? F4: What is the ratio of the actual run time (from question F3 above) to the…
A program sees a 4% miss rate on both the Instruction Cache and the Data Cache. Every instruction requires access to the Instruction cache. Only 35% of the instructions require data access from the Data Cache. The miss penalty for either the data or the instruction cache is 100 cycles. Assume the average Clocks per Instruction (CPI) is 2 without any memory stalls (this is a hypothetical machine where if there were no misses on that instruction, it would get executed in 2 clock cycles. We are not worrying about how it is implemented, just, that suppose it was possible). Assume the number of instructions in a program is X. F3: What is the total run time of the program including the missed cycles dues to data and instruction misses? F4: What is the ratio of the actual run time (from question F3 above) to the fictitious run time if there were no cache misses at all?