In this exercise, we will look at the different ways capacity affects overall performance. In general, cache access time is proportional to capacity. Assume that main memory accesses take 70 ns and that 36% of all instructions access data memory. The following table shows data for L1 Caches attached to each of two processors, P1 and P2, where the L1 hit time defines the P1 and P2 cycle time. Processor L1 Size L1 Miss Rate L1 Hit Time P1 2 KiB 8.0% 0.66 ns P2 4 KiB 6.0% 0.90 ns a. What is the Average Memory Access Time(AMAT) for P1 and P2 (in cycles)? Note, you should take the next larger integer for any fraction of cycles when counting the miss penalty. b. Now you will consider that an L2 cache is added to P1. Use the same L1 cache size, miss rate, and hit time as shown in the previous table. The new L2 cache size, miss rate, and hit time are given below, where L2 miss rate is its local miss rate. Processor L2 Size L2 Miss Rate L2 Hit Time P1 1 MiB 95% 5.62 ns What is the AMAT for P1 with the addition of an L2 cache (in cycles)?
In this exercise, we will look at the different ways capacity affects overall performance. In general, cache access time is proportional to capacity. Assume that main memory accesses take 70 ns and that 36% of all instructions access data memory. The following table shows
data for L1 Caches attached to each of two processors, P1 and P2, where the L1 hit time defines the P1 and P2 cycle time.
Processor L1 Size L1 Miss Rate L1 Hit Time
P1 2 KiB 8.0% 0.66 ns
P2 4 KiB 6.0% 0.90 ns
a. What is the Average Memory Access Time(AMAT) for P1 and P2 (in cycles)? Note, you should take the next larger integer for any fraction of cycles when counting the miss penalty.
b. Now you will consider that an L2 cache is added to P1. Use the same L1 cache size, miss rate, and hit time as shown in the previous table. The new L2 cache size, miss rate, and hit time are given below, where L2 miss rate is its local miss rate.
Processor L2 Size L2 Miss Rate L2 Hit Time
P1 1 MiB 95% 5.62 ns
What is the AMAT for P1 with the addition of an L2 cache (in cycles)?
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