Realize the function f(a, b,c, d) = Em(0,2,5,7,8,10,13,15) (Fonksiyonu gerçekleyiniz!) (a) Use a single 4x1 multiplexer and (if required) a minimum number of additional NAND logic gate(s) (4x1 MUX ve gerekiyorsa en az sayıda VE-DEĞİL kapısı kullanınız) (b) Use 3x8 decoder(s) and (if required) a minimum number of additional NOR logic gate(s) (3x8 KOD ÇÖZÜCŨ ve gerekiyorsa en az sayıda VEYA-DEĞİL kapısı kullanınız)
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- The input to a combinational logic circuit is 4-bit binary number (A, B, C, D). Design the circuit strictly using NAND gate with two outputs (Y1 and Y2) for the following conditions: Output Y1 is low when the input binary number is less than or equal to 7. Output Y2 is high when the input binary number is less than or equal to 7.T: Answer thne f. questions: 1) The hexadecimal number ´Al' has the decimal value equivalent to (A) 80 (B) 161 (C) 100 (D) 101 2) The output of a logic gate is 0 when all its inputs are logic 1. The logic is either (A) a NAND or an EX-OR (B) an OR or an EX-NOR (C) an AND or an EX-OR (D) an NOR or an EX-NOR 3) The Gray code of the Binary number 1100111 is (A) 1011011 (B) 1010100 (C) 1001001 (D) 101101 4) When simplified with Boollean Algebra (a+b)(a+c) simplifies to (A) a (B) a+a(b+c) (C) a(1+bc) (D) a+bc 5) -31 is represented as a sign Binary number ( using Sign-magnitude form ) equal to (A) 00011111 (B) 10101001 (C) 01110010 (D) 00101101 6) The Binary number 110111 is equivalent to decimal number (A) 25 (B) 55 (C) 26 (D) 34 7) With 4 bit, what the range of decimal values if the number is 2's complement signed number. (A) -32 to +31 (B) -2 to +1 (C) -8 to +7 (D) None of theseBelow is an example of an NMOS logic circuit. For all of the MOSFETs in the circuit below, assume V = 1 V and k = 50 mA/V². th W R₂ = 5600 PEETHIPPIN R₁ - 4700 M3 M₁ M. 0 a. Indicate and verify the state of each MOSFET and V for the following input combinations. Fill-out the table below for each assumed state of the MOSFET for every input combination. Use R approximation for linear operation and three significant ds(on) figures for the voltages. 오 Ao SV why
- THE OUTPUT OF A LOGIC GATE IS 1 WHEN ALL ITS INPUTS ARE AT LOGIC 0. THE GATE IS EITHER а. an AND or an X-OR b. a NAND or an X-OR an OR or an X-NOR d. a NOR or an X-NOR3-Using only NOR gates to produce the logic functions of: a-OR gate b - NOTgate c - ANDgate d-NAND gate 4-Determine the output wave form for the cct shown below ,with inputs as shown: A B Dar1. What is the total or equivalent resistance of ten (10) nos of 10-ohm resistors connected in parallel? 2. A single logic gate in a prototype integrated circuit is found to be capable of switching from the “on” state to the “off” state in 12 ps. This corresponds to: a. 1200ns b. 1.2 ns c. 12000 ns d. 120 ns
- 1. Convert 95610 to hexadecimal. 2. Convert 1011.101 base 2 to decimal. 3. Convert 110100112 to decimal number system. 4. Convert 58610 to octal. 5. Convert 10111011012 to octal. (Our lesson is LOGIC CIRCUITS AND SWITCHING THEORY)d) Draw the schematics of 4-bit synchronous and asynchronous MOD-8 counters and comment on their pros and cons. e) Calculate the noise margin for a logic gate with the following logic levels: VIL = 1.1 V, VIH = 3.2 V, VOL = 0.6 V, VOH = 4.0 V.Suppose we have two registers, Rl and R2, and between them we have a combinational logic circuit. The tpcg = 0.5 ns, tccq = 0.25 ns, tpd = 4 ns, tcd = 2.5 ns, tsetup = 0.5 ns and thold = 0.2 ns. What is the maximum value of fc? Select one: a. 0.2 ps O b. 200 MHz O c. 2 GHz O d. 200 KHz
- a) Design a single-digit decade counter that counts from 0 to 9 and repeats. The single-digit decade counter should be built by a cascaded synchronous binary counter (74LS163) and other basic logic gates. Simulate thecomplete counter circuit by OrCAD and PSPICE. Capture the circuit schematic and the simulated waveform.(Define the simulation timings for at least one full counting cycle from 0 to 9 and back to 0.)(Hint: Use the DigClock input from the SOURCE as shown below and setup the CLK ONTIME and OFFTIME accordingly for the clock source.)Instructions A designer at Channel Microsystem needs to design basic logic gates with the use of PN junction diodes, light emitting diodes (LED), 5-V power supply and resistors. The logic gates are to be tested through random input logic pulse and verified in time domain analysis. A O A O Out Out BO BO OR NOR A O Out Out BO в о AND NAND Figure 1 HIGH '1' DIODE-DIODE LOW '0' LOGIC Out GATES во Figure 2 Figure 1 illustrates the combination of logic gates to be developed using diode-diode logic. Figure 2 describes the simulation testbench setup in verifying the operation of the logic gates developed through diode-diode logic. Design and verify the diode-diode logic with low2. a. Assume a 10 bit binary number “0110010111" is stored in a memory. What is its content if it represents i BCD code i1. Excess-3 code iii. 84-2 -1 code