• 6.7 Show how to build each of the following logic functions using one or more 74x138 binary decoders and NAND gates. (Hint: Each realization should be equivalent to a sum of minterms.) • (a) F = E X , Y,Z(2,5,7) o (b) F = II A , B ,C (2,4,5,6,7) o (c) F = E A , B,C,D(0,6,10, 14 ) o (d) F = E W , X , Y , Z (1,4,5,6,11, 12 , 13 , 15 )
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- Design a JKFF by using only a DFF and logic gates. Please design on logisim or handwritingQuestion 1 Design the following circuits by using only 2x1 MUXs and NOT gates. 4X1 MUX 8X1 MUX 2-inputs AND GATE 2-inputs OR GATE Question 2 Design a JKFF by using only a DFF and logic gates. Question 3 Design a sequential modulo 3 accumulators for 2-bit operands. Definition:Accumulator - a circuit that “accumulates” the sum of its input operands over time - it adds each input operand to the stored sum, which is initially 0.Design a code converter that converts a decimal digit from BCD to excess-3 code, the input variables are organized as (A BC D) respectively with A is the MSB, the output variables are organized as (W X Y Z) respectively with W is the MSB, put the invalid decimal numbers as don't care. X= BCD'+B'D+B'C X= BC'D'+B'D+BC X= BC'D'+B'D+B'C X= BC'D'+BD+B'C
- Write a VHDL code for the following simple logic circuit. D- X1 X2 f X3C) DRAW THE LOGIC DIAGRAM CIRCUITS FOR a to g FOR: a1. In the following diagram, you have the architecture of the Intel 8086 questions: Briefly following microprocessor. [CO1/UNDERSTAND] To memory and Input/ Output answer the BIU 6. 5. 4 3. 2 Σ 6-Byte pre-fetch PA Seg X 10H + offset CS SS DS ES IP queue Control Unit EU AH AL AX General BH BL -BX -CX -DX Purpose Registers CH CL DH ALU DL SP ВР SI DI Operands Flags Block Diagram of 8086 Microprocessor Electronics Desk a)Why is the architecture of 8086 divided into two parts? How can the two units enhance the total system performance? b)How many registers are there inside Intel 8086? What is the purpose of segment registers and general-purpose registers? Mention the names also.
- For the state diagram shown below write the state table and design logic circuit 1/0 0/0 00 START FIRST 11 1/1 1/0 SUCCESS SECOND DELAY 1/1 00 0/04- Assume the following input level of parallel full adder A4 A3 A2 A1 Ao = 10010 , B4 B3 B2 B1 Bo =11100 Co 0 What is the logic level at the output of FA2 and FA4? B) 1 and 0 5- Express the decimal number (- 212) in the sign-magnitude forms B) 011010100 A) 0 and 0 C) 1 and 1 D) Not all above A) 111010100 C) 11010100 D) Not all above. 6- (r" - N) to find A) Third complements. 7- Which gate produce 1 out puts when the all inputs are same. A) OR B) Second complements. C) First complements. D) Not all above. B) AND C) EX-OR D) EX-NOR E) Not all above 9 A half adder can be constructed from: - A) Tow XNOR gates only. C) One XOR and one AND gate with their outputs connected in parallel. B) One XOR and one AND gate with their inputs connected in parallel. D) Not all above. 10-What is the weight of the MSB of a 16-bit number? A) (32768)10 B) (65536)10 C) (1)10 D) (2)10 E) None of aboveDesign a code converter that converts a decimal digit from BCD to excess-3 code, the input variables are organized as (A BC D) respectively with A is the MSB, the output variables are organized as (W XY Z) respectively with W is the MSB, put the invalid decimal numbers as don't care. X= BCD'+B'D+B'C X= BC'D'+B'D+BC X= BC'D'+B'D+B'C X= BC'D'+BD+B'C
- Question 1 Design the following circuits by using only 2x1 MUXs and NOT gates. 2-inputs OR GATE Question 2 Design a JKFF by using only a DFF and logic gates. Question 3 Design a sequential modulo 3 accumulators for 2-bit operands. Definition:Accumulator - a circuit that “accumulates” the sum of its input operands over time - it adds each input operand to the stored sum, which is initially 0.Question1: Read the following table, and design a logic circuit that can convert the binary code from 2421 to Excess-3. Four Different Binary Codes for the Decimal Digits Decimal ВCD 8421 Digit 2421 Excess-3 8, 4, –2, –1 0000 0000 0011 0000 1 0001 0001 0100 0111 0010 0010 0101 0110 3 0011 0011 0110 0101 4 0100 0100 0111 0100 5 0101 1011 1000 1011 0110 1100 1001 1010 7 0111 1101 1010 1001 8 1000 1110 1011 1000 1001 1111 1100 1111 1010 0101 0000 0001 Unused 1011 0110 0001 0010 bit 1100 0111 0010 0011 combi- 1101 1000 1101 1100 nations 1110 1001 1110 1101 1111 1010 1111 1110USE DIGITAL LOGIC AND DESIGN Part 1: In Figure_4; we have 4-bit Comparator using 2-bit Comparators block. You have to satisfy given condition by applying all data on figure 4. At the end, given condition should produce HIGH output and other two should be LOW. A3 A2 A1 A0 = 1101 and B3 B2 B1 B0 = 1110 Figure_4 Part 2: The serial data-input waveform (Data in) and data-select inputs (S0 and S1) are shown in Figure_5. Determine the data-output waveforms from D0 through D3. Figure_5 Part 3: Decoder can be useful when we have to decode some specific numbers from their equivalent code. Figure 6 has a concept of 3 to 8 line decoder from which you have to generate output waveform from D0 to D7 with proper relationship to input. Figure_6 Part 4: The data-input and…