Consider the following C code: i-0; while(i<10) { if (i%2=0) {.…..} i = i++; } Assume both the branches(while & if) are indexed to the same location in Branch Targ Buffer(B TB) and the penalties are no clock cycle for correct and one clock cycle fa incorrect prediction (Assume Initial state as NT). i) Evaluate the total number of clock cycles required for the execution of given C code if 2-bit branch predictor is implemented in a computer architecture. i) For the C code determine the total clock cycles if a (3,2) correlation branch predictor i implemented in a computer architecture

Consider the following C code: i-0; while(i<10) { if (i%2=0) {.…..} i = i++; } Assume both the branches(while & if) are indexed to the same location in Branch Targ Buffer(B TB) and the penalties are no clock cycle for correct and one clock cycle fa incorrect prediction (Assume Initial state as NT). i) Evaluate the total number of clock cycles required for the execution of given C code if 2-bit branch predictor is implemented in a computer architecture. i) For the C code determine the total clock cycles if a (3,2) correlation branch predictor i implemented in a computer architecture

C++ for Engineers and Scientists

4th Edition

ISBN:9781133187844

Author:Bronson, Gary J.

Publisher:Bronson, Gary J.

Chapter2: Problem Solving Using C++using

Section2.1: Introduction To C++

Problem 1E: (Practice) State whether the following are valid function names and if so, whether they’re mnemonic...

See similar textbooks

Similar questions

OpenMP C++ With the following code, create 3 versions: Outer loop parallelism: use a single OpenMP pragma only at the outer loop Inner loop parallelism: use a single OpenMP pragma only at the inner loop (use reduction) Nested loop parallelism: use pragmas at both the outer loop and inner loop ----- #pragma omp parallel for for(int i = 0; i < n; i++) { #pragma omp parallel for for(int j = 0; j < n; j++) { y[i] += A[i * n + j] * x[j]; } }
for (i=0; i<1000; i++){ y[i] = w * x[i] + b[i]; } Above C-code has a for loop which will repeat 1000 times of the operation. This code will be running on very simple machine. Change the code to reduce the number of branch instructions. You can have up to 5 lines (statements) within the for loop. What is the number of branch operations before and after?
do { flag[i] = true; turn = i; while (flag[j] && turn == j); Critical section flag[i] = FALSE; Remainder section } Three processes P1, P2, and P3 are sharing a resource R1 in a mutually exclusive manner. Using compare_and_swap instruction, show code for P1, P2, and P3 that shows the entry section and exit section (similar to the code shown in Question 1). Using this code, show a scenario if all three processes want to enter their critical sections.
4.8 For the design entity described below: library ieee; use ieee.std_logic_1164.all; entity myckt is port (a, b, c in std_logic; w, y: out std_logic); end myckt; architecture dataflow of myckt is begin W <= not a or (b and c) ; y <= ((a and b) or c) or (not a and not b); end dataflow; (a) Draw a block diagram of the system with inputs and outputs labeled. (b) Directly translate the architecture to a gate level logic diagram of the circuit (without minimization).
Write a code in sim8085 for the following problem: The pressure of two boilers is monitored and controlled by a microcomputer works based on microprocessor programming. A set of 6 readings of first boiler, recorded by six pressure sensors, which are stored in the memory location starting from 2050H. A corresponding set of 6 reading from the second boiler is stored at the memory location starting from 2060H. Each reading from the first set is expected to be higher than the corresponding position in the second set of readings. Write an 8085 sequence to check whether the first set of reading is higher than the second one or not. If all the readings of first set is higher than the second set, store 00 in the ‘D’ register. If any one of the readings is lower than the corresponding reading of second set, stop the process and store FF in the register ‘D’. Data (H): First set: 78, 89, 6A, 80, 90, 85 Second Set:71, 78, 65, 89, 56, 75
We can change order of operation precedence using
Question 777 electric Program FSM Adder in Verilog (Datapath and controller) have to program that has work like below funtion. (with meely of moore machine) C<=A+B(1 ≤A ≤3) C<=A-B(4 ≤A ≤6) C<=A+2B(A == 7) C<=A-2B(A ≤ 0) Full explain this question and text typing work only thanks
Description: Implement a transistor-level schematic of a computational unit/ALU that can perform the following operations. XOR ● XNOR Multiplication Addition Subtraction ● Rotate Shift Right Magnitude Comparator ● Equality Comparator The computational unit/ALU has a decoder to decode an instruction and a multiplexer to select outputs of different operations. Data inputs are 4-bit wide. Make sure you test your design for all the operations listed above.
1.Express the following functions in sum of minterms and product of maxterms : (a) F (A,B, C,D) = B'D+ A'D+ BD (b) F (x, y, z) = (xy+ z)(xz+ y)
Consider the following C functions and assembly codeAssume that long is 64 bits, int is 32 bits, short is 16 bits, and therepresentation is two’s complement.Assembly Code: imulq %rsi, %rdiimulq %rdx, %rsiaddq %rsi, %rdileaq (%rdi,%rdi,2), %raxsalq $3, %raxret long functionA(long a, long b, long c){long d = a*b;long e = b*c;return 18 * (d+e);} long functionB(long a, long b, long c){long d = a*b;long e = b*c;return 24 * (d*e);} long functionC(long a, long b, long c){long d = a*b;long e = b*c;return 24 * (d+e);} long functionD(long a, long b, long c){long d = a*b;long e = b*c;return 32 * (d*e);} Which of the functions compiled into the assembly code shown?
Do execution paths 3 and 4 encompass the first three conditions for a deadlock to occur?
Select the logic to implement a loop using the LOOPNZ instruction. ECX = ECX – 1 if ECX > 0 and ZF=0 , jump to destination O ECX = ECX + 1 if ECX > 0 and ZF=1, jump to destination EDX = EDX - 1 if EDX < 0 or ZF=0 , jump to destination