4.4 Problems in this exercise assume that logic blocks needed to implement aprocessor's datapath have the following latencies:I-MemAddMuxALURegsD-MemSign-ExtendShift-Left-2200ps70ps20ps-90ps90ps250ps15ps10ps4.4.1. [10] If the only thing we need to do in a processor is fetch consecutiveinstructions (Figure 4.6), what would the cycle time be?4.4.2 [10] Consider a datapath similar to the one in Figure 4.11, but for aprocessor that only has one type of instruction: unconditional PC-relative branch.What would the cycle time be for this datapath?4.4.3 [10] Repeat 4.4.2, but this time we need to support only conditionalPC-relative branches.The remaining three problems in this exercise refer to the datapath element Shift-left-2:4.4.4 [10] Which kinds of instructions require this resource?4.4.5 [20] For which kinds of instructions (if any) is this resource on thecritical path?4.4.6 [10] Assuming that we only support beq and add instructions,discuss how changes in the given latency of this resource affect the cycle time of theprocessor. Assume that the latencies of other resources do not change. 5.8 Mean Time Between Failures (MTBF), Mean Time To Replacement (MTTR), andMean Time To Failure (MTTF) are useful metrics for evaluating the reliability andavailability of a storage resource. Explore these concepts by answering the questionsabout devices with the following metrics.MTTFMTTR3 Years1 Day5.8.1 (5] Calculate the MTBF for each of the devices in the table.5.8.2 [5] Calculate the availability for each of the devices in the table.5.8.3 [5] What happens to availability as the MTTR approaches 0? Is this arealistic situation?5.8.4 [5] What happens to availability as the MTTR gets very high, ie., adevice is difficult to repair? Does this imply the device has low availability?4.2 The basic single-cycle MIPS implementation in Figure 4.2 can only implementsome instructions. New instructions can be added to an existing Instruction SetArchitecture (ISA), but the decision whether or not to do that depends, amongother things, on the cost and complexity the proposed addition introduces into theprocessor datapath and control. The first three problems in this exercise refer to thenew instruction:Instruction: LWI Rt, Rd(Rs)Interpretation: Reg[Rt] -Mem[Reg[Rd]+Reg[Rs]]4.2.1 (10] Which existing blocks (if any) can be used for this instruction?4.2.2 (10] Which new functional blocks (if any) do we need for thisinstruction?4.2.3 (10] What new signals do we need (if any) from the control unit tosupport this instruction?W

Question

4.4 Problems in this exercise assume that logic blocks needed to implement aprocessor's datapath have the following latencies:I-MemAddMuxALURegsD-MemSign-ExtendShift-Left-2200ps70ps20ps-90ps90ps250ps15ps10ps4.4.1. [10] <$4.3> If the only thing we need to do in a processor is fetch consecutiveinstructions (Figure 4.6), what would the cycle time be?4.4.2 [10] <$4.3> Consider a datapath similar to the one in Figure 4.11, but for aprocessor that only has one type of instruction: unconditional PC-relative branch.What would the cycle time be for this datapath?4.4.3 [10] <$4.3> Repeat 4.4.2, but this time we need to support only conditionalPC-relative branches.The remaining three problems in this exercise refer to the datapath element Shift-left-2:4.4.4 [10] <$4.3> Which kinds of instructions require this resource?4.4.5 [20] <$4.3> For which kinds of instructions (if any) is this resource on thecritical path?4.4.6 [10] Assuming that we only support beq and add instructions,discuss how changes in the given latency of this resource affect the cycle time of theprocessor. Assume that the latencies of other resources do not change. 5.8 Mean Time Between Failures (MTBF), Mean Time To Replacement (MTTR), andMean Time To Failure (MTTF) are useful metrics for evaluating the reliability andavailability of a storage resource. Explore these concepts by answering the questionsabout devices with the following metrics.MTTFMTTR3 Years1 Day5.8.1 (5] <$5.5> Calculate the MTBF for each of the devices in the table.5.8.2 [5] <$5.5> Calculate the availability for each of the devices in the table.5.8.3 [5] <$5.5> What happens to availability as the MTTR approaches 0? Is this arealistic situation?5.8.4 [5] <$5.5> What happens to availability as the MTTR gets very high, ie., adevice is difficult to repair? Does this imply the device has low availability?4.2 The basic single-cycle MIPS implementation in Figure 4.2 can only implementsome instructions. New instructions can be added to an existing Instruction SetArchitecture (ISA), but the decision whether or not to do that depends, amongother things, on the cost and complexity the proposed addition introduces into theprocessor datapath and control. The first three problems in this exercise refer to thenew instruction:Instruction: LWI Rt, Rd(Rs)Interpretation: Reg[Rt] -Mem[Reg[Rd]+Reg[Rs]]4.2.1 (10] <$4.1> Which existing blocks (if any) can be used for this instruction?4.2.2 (10] Which new functional blocks (if any) do we need for thisinstruction?4.2.3 (10] <$4.1> What new signals do we need (if any) from the control unit tosupport this instruction?W

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