Assume, paging has been used as memory management technique and the page table is stored in memory which takes 150 nanoseconds. In addition, the associative memory is also used which takes 50 nanoseconds. What is the effective memory reference time, If 50% of all page-table references are found in the associative memory? b, In order to eliminate the need for contiguous allocation of physical memory, paging is assumed as an efficient memory management technique. But in this technique, the user's view of memory is not the same as the actual physical memory, how this could be achieved and how hardware provides such complicated memory translation? (Answer limit max 5 lines)

Assume, paging has been used as memory management technique and the page table is stored in memory which takes 150 nanoseconds. In addition, the associative memory is also used which takes 50 nanoseconds. What is the effective memory reference time, If 50% of all page-table references are found in the associative memory? b, In order to eliminate the need for contiguous allocation of physical memory, paging is assumed as an efficient memory management technique. But in this technique, the user's view of memory is not the same as the actual physical memory, how this could be achieved and how hardware provides such complicated memory translation? (Answer limit max 5 lines)

C++ for Engineers and Scientists

4th Edition

ISBN:9781133187844

Author:Bronson, Gary J.

Publisher:Bronson, Gary J.

Chapter2: Problem Solving Using C++using

Section2.3: Data Types

Problem 9E: (Practice) Although the total number of bytes varies from computer to computer, memory sizes of...

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Assume, paging has been used as memory management technique and the page table is stored in memory which takes 150 nanoseconds. In addition, the associative memory is also used which takes 50 nanoseconds. What is the effective memory reference time, If 50% of all page-table references are found in the associative memory? In order to eliminate the need for contiguous allocation of physical memory, paging is assumed as an efficient memory management technique. But in this technique, the user's view of memory 1s not the same as the actual physical memory, how this could be achieved and how hardware provides such complicated memory translation? (Answer limit max 8 lines) SHOT ON POCO M3 2021.2.12 21:23
Assume, paging has been used as memory management technique and the page table is stored in memory which takes 150 nanoseconds. In addition, the associative memory is also used which takes 50 nanoseconds. What is the effective memory reference time, If 50% of all page-table references are found in the associative memory? In order to eliminate the need for contiguous allocation of physical memory, paging is assumed as an efficient memory management technique. But in this technique, the user's view of memory is not the same as the actual physical memory, how this could be achieved and how hardware provides such complicated memory translation?
Please help with a, b, and c: Consider a virtual memory system that uses paging and a translation lookaside buffer (TLB) to cache the most recent virtual page-to-physical page translations. The following assumptions are made: The memory is byte addressable. Memory accesses are to 4-byte words. Virtual addresses are 20 bits wide. Physical addresses are 16 bits wide. The page size is 4096 bytes. The TLB is 4-way set associative with 16 total entries. The contents of the TLB and the page table for the first 32 pages are shown in the figure below: TLB Page Table Index Tag PPN Valid VPN PPN Valid VPN PPN Valid 0 03 B 1 00 7 1 10 6 0 07 6 0 01 8 0 11 7 0 28 3 1 02 9 1 12 8 0 01 F 0 03 A 1 13 3 0 1 31 0 1 04 6 0 14 D 0 12 3 0 05 3 0 15 B 0 07 E 1 06 1 0 16 9 0…
c. In a dynamic partitioning approach for memory management we could use a bitmap or a linked list to keep track of free and used memory. i. Briefly explain why linked lists are normally the preferred option. ii. Briefly explain a situation where bitmaps may be preferred. iii. Briefly explain the working of the best fit algorithm to allocate processes to memory when dynamic partitioning is used. iv. Does the best fit algorithm result in external fragmentation? v. Does the worst fit algorithm result in internal fragmentation?
a) Assume, paging has been used as memory management technique and the page table is stored in memory which takes 150 nanoseconds. In addition, the associative memory is also used which takes 50 nanoseconds. What is the effective memory reference time, If 50% of all page-table references are found in the associative memory?
4. The following is the memory configuration at a given point in time where dynamic partitioning scheme is used. The shaded areas indicate memory spaces already allocated to other processes, while the white spaces are holes (free memory spaces). The next FOUR (4) memory requests are 30M, followed by 50M, 20M and 40M (in order). Shade and indicate clearly which memory block will be allocated to each request using the first- fit and next-fit placement algorithms. (First-fit) 20M (Best-fit) 20M (Next-fit) 20M 80M 1 2 3 4 80M 80M b. Given a process segment table as follows: Segment 0 (X is the lastest allocated block) 20M Base 496 1202 232 2359 1877 20M 20M Length 691 85 198 109 258 50M 50M 50M 10M 10M 10M X 30M 30M 30M Explain the basic use of segment table in process segmentation and its difference with paging. Give one example on how the information in the given process segment table is used.
4. The following is the memory configuration at a given point in time where dynamic partitioning scheme is used. The shaded areas indicate memory spaces already allocated to other processes, while the white spaces are holes (free memory spaces). The next FOUR (4) memory requests are 30M, followed by 50M, 20M and 40M (in order). Shade and indicate clearly which memory block will be allocated to each request using the first- fit and next-fit placement algorithms. (First-fit) 20M (Best-fit) 20M (Next-fit) 20M 80M 80M 20M 80M 20M (X is the lastest allocated block) 20M 50M 50M 50M 10M 10M 10M X 30M 30M 30M
6. A cache has the following parameters: b, block size given in numbers of words; S, number of sets; N, number of ways;and A, number of 页2 address bits.A 16-word cache has the parameters given above. Consider the following repeating sequence of lw addresses (given in hexadecimal) and cache con.gurations: 74 A0 78 38C AC 84 88 8C 7C 34 38 13C 388 18C The cache capacity is still 16 words. Assuming least recently used (LRU) replacement for associative caches, determine the efective miss rate if the sequence is input to the following caches, ignoring startup effects (i.e., compulsory misses) (1) two-way set associative cache, b = 2 words (2) direct mapped cache, b= 4 words
In an mxn matrix, where the row index varies from 1 to m and column index from 1 to n, aij denotes the number in the h row and the jh column. In the computer's memory, all elements are stored linearly using contiguous addresses. Therefore, to store a two-dimensional matrix, two-dimensional address space must be mapped to one- dimensional address space. In the computer's memory, matrices are stored in either row-major order or column- Column-major order major order form. In row-major order, the consecutive elements of a row reside next to each other. In column- major order, the consecutive elements of a column reside Row-major order a a12 a13 a22 a23 с. a1 a12 a3 a22 a23 [5 1] 4 3 6 8 l2 7] 81 next to each other. Consider the matrix A = Base address of the matrix is 3FA2H. Each element is stored in 2 bytes. Each memory location is one byte long. i. Give the addresses of 4 and 8 if the matrix is stored in row-major order. ii. Give the addresses of 3 and 2 if the matrix is stored in…
Question 2: This diagram shows an example of memory configuration under dynamic partitioning, after a number of placement and swapping-out operations have been carried out. Addresses go from left to right; gray areas indicate blocks occupied by processes; white areas indicate free memory blocks. The last process placed is 2-Mbyte and is marked with an X. Only one process was swapped out after that. 4M M X 5M 8M 2M 4M 3M a. What was the maximum size of the swapped-out process? b. What was the size of the free block just before it was partitioned by X? C. A new 3-Mbyte allocation request must be satisfied next. Indicate the intervals of memory where a partition will be created for the new process under the following four placement algorithms: best-fit, first-fit, next-fit, worst-fit. For each algorithm,
• Perform capacity planning for a two level memory hierarchy system. The first level, M, is a cache with three capacity choices 64 Kbytes, 128 Kbytes and 256 Kbytes. The second level, M, is a main memory with a 4 Mbyte capacity. Let C, and C, be the cost per byte and t, and t, the access times for M, and M, respectively. Assume C,=20C, and t,=10t,- The cache hit ratios for the three capacities are assumed to be 0.7, 0.9 and 0.98 respectively. i) What is the average access time t, in terms of t,=20ns in the three cache designs? ассе ii) Express the average byte cost of the entire memory hierarchy if C,=$0.2/Kbyte. iii) Compare the three memory designs and indicate the order of merit in terms of average costs and average access times respectively. Choose the optimal design based on the product of average cost & average access times.
As discussed in the class for main memory hierarchy to work correctly, the main memory is mappedon to the cache memory. Some of the mapping techniques are direct, fully associative and setassociative. The key design parameters are: sizes of main and cache memory, lines (blocks) in thecache, blocks in the main memory and mapping function. For this question, let us assume that thesize of main memory is 16Mbytes, the size of cache is 16kbytes and the size of the block is 32 bytes.i. How many bits are needed for the main memory? How many bits among them are neededfor block number and block offset?ii. How many bits are needed for the cache memory? How many lines are there and how manybits are needed to identify this? What will be the block offset?iii. How many tag bits are needed if the memory uses fully-associative and two-way (set size of2) set-associative cache?iv. Draw diagram to show the fully-associative and two-way (set size of 2) set-associative cachemapping. Which one is better and…