A system with 64GB memory with a block size of 4 words, and a 256KB direct map cache. The word size is 2 bytes. What is the number of address bits reserved for the Line number field? O 16 O 11 O 18 O 15 What is the number of bits reserved for the Tag field? O 20 O 36 O 33 18 The main memory block # 4095 (in decimal) will directly map to cache line? O 1023 O 1 4095 O 2047 The number of address lines the memory has is O 32 O 35 O 31 O 26

A system with 64GB memory with a block size of 4 words, and a 256KB direct map cache. The word size is 2 bytes. What is the number of address bits reserved for the Line number field? O 16 O 11 O 18 O 15 What is the number of bits reserved for the Tag field? O 20 O 36 O 33 18 The main memory block # 4095 (in decimal) will directly map to cache line? O 1023 O 1 4095 O 2047 The number of address lines the memory has is O 32 O 35 O 31 O 26

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter6: System Integration And Performance

Section: Chapter Questions

Problem 6VE

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Similar questions

A cache is set up with a block size of 32 words. There are 64 blocks in cache and set up to be 4-way set associative. You have byte address 0x8923. Show the word address, block address, tag, and index Show each access being filled in with a note of hit or miss. You are given word address and the access are: 0xff, 0x08, 0x22, 0x00, 0x39, 0xF3, 0x07, 0xc0.
Assume a cache system has been designed such that cach block contains 4 words and the cache has 1024 lines, the cache can store up 10 1024 blocks. What line of the cache is supposed 10 hold the block that contains the word from the twenty-bit address JA456:? In addition, what is the tag number that will be stored with the block?
A computer using direct mapping cache has 256Mbytes of byte addressable main memory and cache size of 32k lines and each cache block contain 8 bytes. How many blocks of main memory are there?What are the size of the tag, line number and words?To which cache block will the memory address 13ADEF9H map?To which line number will the memory address 17FEAD8H map?
Suppose a computer using direct mapped cache has 236 bytes of byte-addressable main memory and a cache size of 1024 bytes, and each cache block contains 64 bytes. ⦁ How many blocks of main memory are there? ⦁ What is the format of a memory address as seen by cache, i.e., what are the sizes of the tag, block, and offset fields? ⦁ To which cache block will the memory address 0x13A4576B map?
Suppose a computer using direct mapped cache has 232 words of main memory, and a cache of 1024 blocks, where each cache block contains 32 words. How many blocks of main memory are there? What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag, block, and offset fields? To which cache block will the memory reference 0003101A16 map?
A machine uses 32 bit addressing. A direct-mapped cache with one word (4 bytes makes a word) per block (one word per cache line) exists in the machine. The address requires 12 Index bits and 2 bits for byte offset are ignored for addressing. The SRAM has 1 Valid bit per memory location. H1: What is the total number of bitcells required in this SRAM (include all bits needed for data, tag and valid bit)? H2: If the number of cache lines is doubled (the number of words that can be saved is doubled), what would be the new number of bits stored in the SRAM?
A computer system has a 128 byte cache. It uses four-way set-associative mapping with 8 bytes in each block. The phy 32 bits, and the smallest addressable unit is 1 byte. (i) To what block frames of the cache can the address 000010AFH be assigned? (ii) If the addresses 000010AFH and FFFF7AXYH can be simultaneously assigned to the same Cache set, what values digits X and Y have?
If you know that: Tag = 8 bits, Line = 14 bits, and Word= 2 bits for a direct- mapped cache. For the hexadecimal main memory addresses, 888888, what is the value of the "word" field , in hexadecimal format.
For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. We assume that each word has 4 bytes. How many entries does the cache have? Tag Index Offset Block offset | Byte offset 31–12 11-6 5-2 1-0
Suppose a computer using fully associative cache has 220220 words of main memory and a cache of 128 blocks, where each cache block contains 16 words. (a) How many blocks of main memory are there? (b) What is the format of a memory address as seen by the cache, that is, what are the sizes of the tag and word fields? (c) To which cache block will the memory reference 01D872_{16}01D872_{16} map?
A cache is set up with a block size of 32 words. There are 16 blocks in cache and set up to be direct map. You have byte address 0x8923. Show the word address, block address, tag, and index. Show each access being filled in with a note of hit or miss. You are given word address and the access are: 0xff, 0x08, 0x22, 0x00, 0x39, 0xF3, 0x07, 0xc0
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