multi-level paging used by a process that has following: a. Logical Address = 64 bits b. Page size = 1 M Byte c. Page table entry size = 4 Byte d. System is byte addressable. calculate the following. 1. Logical Address Space? 2. Maximum number of page table entries in a single page? 3. How many levels of page table entries will be used?
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A:
Assume the following scenario for multi-level paging used by a process that has following:
a. Logical Address = 64 bits
b. Page size = 1 M Byte
c. Page table entry size = 4 Byte
d. System is byte addressable.
calculate the following.
1. Logical Address Space?
2. Maximum number of page table entries in a single page?
3. How many levels of page table entries will be used?
4. Compute the size of page tables at each level?
5. Compute the number of entries in a single page?
6. Compute the number of pages
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Solved in 2 steps
- Suppose we have a computer system with 44-bit logical addresses, page size of 64KiB, and 4 bytes per page table entry. b. Suppose we use two-level paging and arrange for all page tables to fit into a single page frame. How will the bits of the address be divided up? (show your work) c. Suppose we have a program with a 4GiB address space. Counting the program and all page tables, using the two-level page table scheme from the previous question, how much memory, in number of page frames, is used? (show your work)Computer Science 9. In a paging system , the logical address is formed of 20 bits. the most significant 8 bits denote the page number, the least significant 12 bits denote the offset. Memory size is 256K bits. a. What is the page size (in bits)? b. What is the maximum number of pages per process? c. How many frames does this system have? d . Give the structure of the page table of a process executing in this system. Assume 2 bits are reserved for attributes. e. How many bits are required for each page table entry? f. If physical memory is upgraded to 1024 K bits, how will your answer to c and e change?Consider a paged virtual memory system with 32-bit virtual addresses and 1K-byte pages. Each page table entry requires 32 bits. It is desired to limit the page table size to one page. a. How many levels of page tables are required? b. What is the size of the page table at cach level? Hint: One page table size is smaller. c. The smaller page size could be used at the top level or the bottom level of the page table hierarchy. Which strategy consumes the least number of pages?
- Consider a paging system with the following: Physical memory= 32 bytes. Page size=4 bytes. Page Table: Page Frame 0 5 1 6 2 1 3 2 What are the physical addresses for the following logical addresses? A) 15 B) 8 C) 4Suppose a computer system uses 16-bit addresses for both its virtual and physical addresses. In addition, assume each page (and frame) has size 256 bytes. How many bits are used for the page number? How many bits are used for the offset? 8 bits each. With this system, what’s the maximum number of pages that a process can have? 256 Suppose that each entry in the page table comprises 4 bytes (including the frame number, the valid bit, and miscellaneous “bookkeeping bits”). An OS uses an array to store the page table. What is the size of the page table? 1024 Bytes Furthermore, suppose the first 6 pages of a process map to frames 222 to 227 (as decimal numbers), and the last 5 pages of the process map to frames 1 to 5 (also decimal numbers). All other pages are invalid. Draw the page table, including the valid bit and the frame number. DONE Translate the following virtual addresses to physical addresses, and show how you obtain the answers. (Hint: You do not need to convert…Consider an operating system that uses 48-bit virtual addresses and 16KB pages. The system uses a multi-level page table design to store all the page table entries of a process, and each page table entry and index entry are 4 bytes in size. What is the total number of page that are required to store the page table entries of a process, across all levels of the page table? You may follow the hint below or finish from scratch to fill the blanks. Please show your calculations to get partial points like 2^10/2^4=2^6. 1. We need to calculate the total number of page table entries needed for a process (i.e., the total number of pages for a process) 2. We need to calculate how many entries each page can store 3. With 1 and 2, we can calculate how many pages needed for the lowest (innermost) level 4. Each page from 3 requires an entry (pointer) in the upper (next) level. We need to calculate how many pages are required to store this next level entries (please note the entry size is always 4…
- 9. Consider a system that uses 32-bit addresses and page table structures as discussed in class. If the address space of a process contains exactly 256 pages, what is the minimum number of pages that might be needed for its page table structure? What is the maximum number that might be needed? Briefly explain your answer.On a simple paging system with 224 bytes of physical memory, 256 pages of logical address space, and a page size of 210 bytes. 1. How many bits are needed to store an entry in the page table (how wide is the page table)? Assume a valid/invalid 1-bit is included in each entry. 2. If the page table is stored in the main memory with 250nsec access time, how long does a paged memory reference take? 3. If the page table is implemented using associative registers that takes 95nsec. and main memory that takes 200nsec, what is the total access time if 75% of all memory references find their entries in the associative registers?Consider a computer system with a 30-bit logical address and 4-KB page size. The system supports up to 512 MB of physical memory. How many entries are there in each of the following? Assume that each page table entry is 4 Bytes. c. A conventional single-level page table?d. An inverted page table?e. A two-level hierarchical page table? Consider a virtual memory system with a 50-bit logical address and a 38-bit physical address. Suppose that the page/frame size is 16K bytes. Assume that each page table entry is 4 Bytes. a. How many frames are in the systems? How many pages in the virtual address space for a process? b. If a single-level page table is deployed, calculate the size of the page table for each process. c. Design a multilevel page table structure for this system to ensure that each page table can fit into one frame. How many levels do you need? Draw a figure to show your page systems
- Suppose a computer using 8-way set associative cache has 1 M words of main memory, and a cache of 16 K words, where each cache block contains 8 words. What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag, set, and ?word fields Tag = 9-bit, Set = 8-bit, Word = 3-bit Tag = 9-bit, Set = 7-bit, Word =4-bit Tag = 9-bit, Set = 6-bit, Word = 5-bit Tag = 9-bit, Set = 5-bit, Word = 6-bitConsider a computer system with a 30-bit logical address and 4-KB page size. The system supports up to 512 MB of physical memory. How many entries are there in each of the following? Assume that each page table entry is 4 Bytes. A conventional single-level page table? An inverted pagetable? A two-level hierarchical page table?Suppose a computer system uses 16-bit addresses for both its virtual and physical addresses. In addition, assume each page (and frame) has size 256 bytes. How many bits are used for the page number? How many bits are used for the offset? With this system, what’s the maximum number of pages that a process can have? Suppose that each entry in the page table comprises 4 bytes (including the frame number, the valid bit, and miscellaneous “bookkeeping bits”). An OS uses an array to store the page table. What is the size of the page table? Furthermore, suppose the first 6 pages of a process map to frames 222 to 227 (as decimal numbers), and the last 5 pages of the process map to frames 1 to 5 (also decimal numbers). All other pages are invalid. Draw the page table, including the valid bit and the frame number.