ARP and DNS both depend on caches; ARP cache entry lifetimes are typically 10 minutes, while DNS cache lifetimes are on the order of days. Justify this difference. What undesirable consequences might there be in having too long a DNS cache entry lifetime?
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- For a physically Indexed L1D cache, what is the average read latency if TLB hit rate is 99.5% and the L1 data cache hit rate is 98%? Assume TLB hit latency: 0.5 nS, L1D hit latency: 1ns, L2 hit latency: 10nS. Assume L2 hit rate is 100% and page tables are cached.In a network scenario, access link rate is 2 Mbps, RTT from the company router to server is 2 sec and web object size is 100K bits. If the average request rate from browsers to origin servers is 18 requests per second, what is the access link utilization? What are the problems associated with high link utilization? If a cache server with hit rate of 60% is used, what is the access link utilization?Your explanation of the inner workings of one of the cache protocols would be very appreciated.
- What is the difference between a Routing and a Paging cache?The total number of bits within a certain fully associative cache is 2056 Kibit. The cache stores 1024 blocks. Each block has 64 words and each word is 4 bytos Calculate the size of the tag field and the size of the address generated by the processor, in bits. Notice, the address is not necessarily 32-bit. bits. Size of the tag field = Size of the address = bits الرجاء إدخال النتيجة بدون مسافة أو وحدة 10 of 16Offer a succinct explanation of one of the cache protocols in use.
- If you could describe how one of the cache protocols is utilized in its intended way, that would be incredibly beneficial.Please provide a concise overview of one of the cache protocols currently in existence?A computer system has a 128 byte cache. It uses four-way set-associative mapping with 8 bytes in each block. The phy 32 bits, and the smallest addressable unit is 1 byte. (i) To what block frames of the cache can the address 000010AFH be assigned? (ii) If the addresses 000010AFH and FFFF7AXYH can be simultaneously assigned to the same Cache set, what values digits X and Y have?
- How does a totally associative cache work?Given a 2-way set-associative cache with 2 entries (sets) and 1 byte block size (no offset), what is the LRU value of each entry (set) after the following processor access sequence? Assume the LRU bits of both entries are set to 0 initially. Processor accesses: 10000, 10001, 11101, 11011, 11110 LRU (entry 0) = _, LRU (entry 1) = O 1,0 O 0, 0 O 0, 1 O 1, 1I would appreciate it if you could describe how one of the cache protocols works within.