A process contains 8 virtual pages on the disk, and is assigned a fixed allocation of 4 page frames in the main memory . The following page trace occurs: 1, 0, 2, 2, 1, 7, 6, 7, 0, 1, 2, 0, 3, 0, 4, 5, 1, 5, 2, 4, 5, 6, 7, 6, 7, 2, 4, 2, 7, 3, 3, 2, 3 1.Show the successive pages residing in the four frames using the LRU replacement policy. Compute the hit ratio in main memory. Assume that the frames are initially empty. 2.Repeat part (a) for the FIFO replacement policy. 3Compare the two hit ratios and comment on the effectiveness of using FIFO to approximate LRU with respect to this particular trace.

A process contains 8 virtual pages on the disk, and is assigned a fixed allocation of 4 page frames in the main memory . The following page trace occurs: 1, 0, 2, 2, 1, 7, 6, 7, 0, 1, 2, 0, 3, 0, 4, 5, 1, 5, 2, 4, 5, 6, 7, 6, 7, 2, 4, 2, 7, 3, 3, 2, 3 1.Show the successive pages residing in the four frames using the LRU replacement policy. Compute the hit ratio in main memory. Assume that the frames are initially empty. 2.Repeat part (a) for the FIFO replacement policy. 3Compare the two hit ratios and comment on the effectiveness of using FIFO to approximate LRU with respect to this particular trace.

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter11: Operating Systems

Section: Chapter Questions

Problem 26VE

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In a main memory-disk virtual storage system, the page size is 1KByte and the FIFO algorithm is used for page replacements. A given program has been allocated three page frames in the main memory and it makes the following 16 memory references when it starts executing (the addresses are given in decimal):500, 2000, 2500, 800, 4000, 1000, 5500, 1500, 2800, 400, 5000, 700, 2100, 3500, 900, 2400 Fill in the contents of the three page frames after each memory reference in a table and calculate the hit ratio. Hint: denote by 'a' the page consisting of locations 0 through 1023 in memory. Similarly, b: 1024-2047, c: 2048-3071, d: 3072-4095, e: 4096-5119 and f: 5120-6143. Round to three decimal places.
In a main memory-disk virtual storage system, the page size is 1KByte and the OPTIMAL algorithm is used for page replacements. A given program has been allocated three page frames in the main memory and it makes the following 16 memory references when it starts executing (the addresses are given in decimal):500, 2000, 2500, 800, 4000, 1000, 5500, 1500, 2800, 400, 5000, 700, 2100, 3500, 900, 2400 Fill in the contents of the three page frames after each memory reference in a table and calculate the hit ratio. Hint: denote by 'a' the page consisting of locations 0 through 1023 in memory. Similarly, b: 1024-2047, c: 2048-3071, d: 3072-4095, e: 4096-5119 and f: 5120-6143. Round to three decimal places.
If a program has 471 bytes and will be loaded into page frames of 126 bytes each, assuming the job begins loading at the first page (Page 0) in memory, and the instruction to be used is at byte 132, answer the following questions: a. How many pages are needed to store the entire job? b. Compute the page number and exact displacement for each of the byte addresses where the desired data is stored.
In the S/370 architecture, a storage key is a control field associated with each page- sized frame of real memory. Two bits of that key that are relevant for page replace- ment are the reference bit and the change bit. The reference bit is set to 1 when any address within the frame is accessed for read or write, and is set to 0 when a new page is loaded into the frame. The change bit is set to 1 when a write operation is per- formed on any location within the frame. Suggest an approach for determining which page frames are least-recently-used, making use of only the reference bit.
Suppose a virtual memory address is 0x123456789012. Divide this address into the 4 different page table parts and the within page offset.
In a certain computer, the virtual addresses are 32 bits long and the physical addresses are 48 bits long. The memory is word addressable. The page size is 16 kB and the word size is 2 bytes. The Translation Look-aside Buffer (TLB) in the address translation path has 64 valid entries. Hit ratio of TLB is 100% then maximum number of distinct virtual addresses that can be translated is K.
The effective access time in a virtual memory system depends on the TLB hit rate but does not depend on whether the page table contains a valid translation for the page. O True O False
In a system where a single-level page table is maintained and no other support mechanism exists, exactly two memory accesses will be required to complete the process of adding a constant number to a value in a register of the CPU. (a) True (b)False
What is Translation Look-Aside Buffer used in paging? answer a)It is a memory that is searched when a page is not found in page table b)It is part of the physical memory to hold process control blocks c)It is a bank of special registers inside the processor d)It is an associative memory that can do parallel frame search in hardware
True/False During the 'READ' of the SRAM structure studied in the class, the bit and bit_bar are both precharged to a high, and then the word line is turned high. This will always result in one of the bit or the bit_bar lines to start tending to go low, while the other remains at the precharged levels.
5. Ifa program has 956 bytes and will be loaded into page frames of 150 bytes each, and the instruction to be used is at byte 332, answerthe following questions: a. How many pages are needed to store the entire job? b. Compute the page numberand exact displacement for each of the byte addresses where the data is stored. (Remember that page numbering starts at zero).
Read-only memory (usually known by its acronym, ROM) is a class of storage media used in computers and other electronic devices that is non-volatile (non-changeable). Because data stored in ROM cannot be modified (at least not very quickly or easily), it is mainly used to distribute firmware (software that is very closely tied to specific hardware, and unlikely to require frequent updates). Figure 3.1 depicts a ROM block diagram which have k-bit address and an n-bit data. The contents of a ROM chip are defined once. Hence, we can use a constant array to model a ROM in VHDL. Basically, to name the size of a ROM is by stating ROM k x n, which represents ROM with k-bit address andn-bit data size. For example, ROM 4x8 (16 address location with each location containing 8-bit data). Question. Develop a code to allow the ROM operation works in synchronous when a read enable is asserted.• Generate and simulate the VHDL codes in Altera Quartus II.• Demonstrate and obtain the instructor…