In a certain computer, the virtual addresses are32 bits long and the physical addresses are 48bits long. The memory is word addressable. Thepage size is 16 kB and the word size is 2 bytes.The Translation Look-aside Buffer (TLB) in theaddress translation path has 64 valid entries. Hitratio of TLB is 100% then maximum number ofdistinct virtual addresses that can be translatedisK.

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Engineering

Computer Science

address I addres rd size ffer (TI 64 valid

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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physcal addresses are 4s ng 4 Ame dat in a cetain compe, te addresses can be translaled without y TLB entries At most how many ditina vid the address translation peh has 12 vld The Translation Look aside Bulfer (TLB)i sine is kB and the word size iby The memory is word addresible. The pe virtual addresses are 64 bea long d th sine is miss?
In a main memory-disk virtual storage system, the page size is 1KByte and the FIFO algorithm is used for page replacements. A given program has been allocated three page frames in the main memory and it makes the following 16 memory references when it starts executing (the addresses are given in decimal):500, 2000, 2500, 800, 4000, 1000, 5500, 1500, 2800, 400, 5000, 700, 2100, 3500, 900, 2400 Fill in the contents of the three page frames after each memory reference in a table and calculate the hit ratio. Hint: denote by 'a' the page consisting of locations 0 through 1023 in memory. Similarly, b: 1024-2047, c: 2048-3071, d: 3072-4095, e: 4096-5119 and f: 5120-6143. Round to three decimal places.
Memory address Data According to the memory view given below, if RO = Ox20008002 then LDRSB r1, [r0, #-4] is executed as a result of r1 = ?(data overlay big endian)? Øx20008002 ØXA1 Øx20008001 ØXB2 Øx20008000 Øx73 ØX20007FFE ØXD4 ØX20007FFE Lütfen birini seçin: O A. R1 = 0X7F O B. R1 = Oxffffffd4 O C. R1 = Oxffffff7F O D. R1=0XD4000000 O E. R1 = 0XD4
Code a descriptor that describes a data memory segment that grows upward and begins at location 03000000H and ends at location 05FFFFFFH and can be written. The memory has not been accessed, and can be accessed with the lowest privilege level. Assume that the segment is available (i.e., AV=1) and that the instructions are 32 bits (i.e., D=1).
In the S/370 architecture, a storage key is a control field associated with each page- sized frame of real memory. Two bits of that key that are relevant for page replace- ment are the reference bit and the change bit. The reference bit is set to 1 when any address within the frame is accessed for read or write, and is set to 0 when a new page is loaded into the frame. The change bit is set to 1 when a write operation is per- formed on any location within the frame. Suggest an approach for determining which page frames are least-recently-used, making use of only the reference bit.
Design a memory map to work with 8085 Microprocessor to have 8K byte ROM and 2K byte RAM. ROM should start from memory location 0000H and RAM immediately follows it. Use exhaustive decoding scheme?
A cache is set up with a block size of 32 words. There are 64 blocks in cache and set up to be 4-way set associative. You have byte address 0x8923. Show the word address, block address, tag, and index Show each access being filled in with a note of hit or miss. You are given word address and the access are: 0xff, 0x08, 0x22, 0x00, 0x39, 0xF3, 0x07, 0xc0.
In a main memory-disk virtual storage system, the page size is 1KByte and the OPTIMAL algorithm is used for page replacements. A given program has been allocated three page frames in the main memory and it makes the following 16 memory references when it starts executing (the addresses are given in decimal):500, 2000, 2500, 800, 4000, 1000, 5500, 1500, 2800, 400, 5000, 700, 2100, 3500, 900, 2400 Fill in the contents of the three page frames after each memory reference in a table and calculate the hit ratio. Hint: denote by 'a' the page consisting of locations 0 through 1023 in memory. Similarly, b: 1024-2047, c: 2048-3071, d: 3072-4095, e: 4096-5119 and f: 5120-6143. Round to three decimal places.
Paging: Select all of the following statements that are true. Systems that use paging but do not support inverted page tables maintain at least one separate page table for each process. The frame table is a system-wide data structure. When paging is applied, the selected page size determines which part of a virtual address belongs to the page number and which to the offset. The page size may differ from the frame size. The Translation Look-aside Buffer (TLB) represents a page directory for all pages in the system. Paging is prone to internal fragmentation.
Create a program in C++ which simulates a direct cache. The memory array that contains the data to becached is byte addressable and can contain 256 single byte entries or lines. The cache has only 8 entriesor lines. The Data field in each line of the cache is 8 bits. Since the data stored in each line of the cache isonly 8 bits, there is no need for a line field. Only a tag field is needed which is log2(256) = 8 bits.The memory array can be filled with any values of your choice. The program should work by taking userinput of a memory address (index). This input represents the memory data that should be cached.Check the cache to see if the item is already cached. If it is not, your program should counta cache miss, and then replace the item currently in the cache with the data from the inputted address.Allow the user to input addresses (in a loop), until they so choose to end the program. The program should output the number of cache misses upon ending.
Code a descriptor that describes a memory segment that begins at location 0005CF00h and ends at location 00060EFFh. The memory segment is a data segment that grows upward in the memory system and can be written. The segment has a user level privilege (lowest) and has not been accessed. The descriptor is for an 80386 microprocessor.
Code a descriptor that describes a memory segment that begins at location AB208000H and ends at location AC20AFFFH. The memory segment is a data segment that grows upward and can be written. The instruction used is a 32-bit size. it is assumed that the privilege level of the segment was set at 2nd highest and that the segment has not been accessed.