1. Assume that L1 cache can be written with 16bytes every 4 processor cycle, the time to receive the first 16 byte block from the memory controller is 120 cycles, each additional 16 byte block from main memory requires 16 cycles and data can be bypassed directly into the read port of the L1 cache. How many cycles would it take to service an L1 cache miss.

1. Assume that L1 cache can be written with 16bytes every 4 processor cycle, the time to receive the first 16 byte block from the memory controller is 120 cycles, each additional 16 byte block from main memory requires 16 cycles and data can be bypassed directly into the read port of the L1 cache. How many cycles would it take to service an L1 cache miss.

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter6: System Integration And Performance

Section: Chapter Questions

Problem 6VE

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Consider a single-level cache with an access time of 2 ns, a line size of 64 bytes, and a hit ratio H=0.94. Main memory uses a block transfer capability that has a first-word (4 bytes) access time of 40ns and an access time of 5ns for each word thereafter. (a) What is the access time when there is a cache miss? Assume that the cache waits until the line has been fetched from main memory and then re-executes for a hit. (b) Suppose that increasing the line size to 128 bytes increases the H to 0.97. Does this reduce the average memory access time?
1. Assume that L1 cache can be written with 16 bytes every 4 processor cycle, the time to receive the first 16 byte block from the memory controller is 120 cycles, each additional 16 byte block from main memory requires 16 cycles and data can be bypassed directly into the read port of the L1 cache. How many cycles would it take to service an L1 cache miss.
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A cache memory system with capacity of N words and block size of B words is to be designed. If it is designed as a direct mapped cache, the length of the TAG field is 14 bits. If it is designed as a 4-way set associative cache, the length of the TAG field will be ………… bits.
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