C1. Consider a main memory with size 4GB with cache size 16 KB and memory block is 8 bytes. Assume that the memory word is 1 byte. Answer the following questions: a. How many address bits are required to address the main memory locations? b. How many lines are there in the cache memory? c. Determine how to split the address (s-f, 1, w) for direct mapping. d. Determine how to split the address (s-d, d, w) for set associative mapping. Assume each cache set is 2 lines of cache.

Computer Networking: A Top-Down Approach (7th Edition)
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Author:James Kurose, Keith Ross
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Chapter1: Computer Networks And The Internet
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C1. Consider a main memory with size 4GB with cache size 16 KB and memory block is 8 bytes.
Assume that the memory word is 1 byte. Answer the following questions:
a. How many address bits are required to address the main memory locations?
b. How many lines are there in the cache memory?
c. Determine how to split the address (s-r, r, w) for direct mapping.
d. Determine how to split the address (s-d, d, w) for set associative mapping. Assume each cache
set is 2 lines of cache.
Transcribed Image Text:C1. Consider a main memory with size 4GB with cache size 16 KB and memory block is 8 bytes. Assume that the memory word is 1 byte. Answer the following questions: a. How many address bits are required to address the main memory locations? b. How many lines are there in the cache memory? c. Determine how to split the address (s-r, r, w) for direct mapping. d. Determine how to split the address (s-d, d, w) for set associative mapping. Assume each cache set is 2 lines of cache.
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