Question 1 Consider a memory system that uses a 32-bit address at the byte level, plus a cache that uses a 64-byte line size. a)Assume a direct mapped cache with a tag field in the address of 20 bits. Show the address format and determine the following parameters: number of addressable units, number of blocks in main memory, number of lines in cache, size of tag b) Assume an associative cache. Show the address format and determine the following parameters: number of addressable units, number of blocks in main memory, number of lines in cache, size of tag. c) Assume a four-way set-associative cache with a tag field in the address of 9 bits. Show the address format and determine the following parameters: number of addressable units, number of blocks in main memory, number of lines in set, number of sets in cache, number of lines in cache, size of tag.

Question 1 Consider a memory system that uses a 32-bit address at the byte level, plus a cache that uses a 64-byte line size. a)Assume a direct mapped cache with a tag field in the address of 20 bits. Show the address format and determine the following parameters: number of addressable units, number of blocks in main memory, number of lines in cache, size of tag b) Assume an associative cache. Show the address format and determine the following parameters: number of addressable units, number of blocks in main memory, number of lines in cache, size of tag. c) Assume a four-way set-associative cache with a tag field in the address of 9 bits. Show the address format and determine the following parameters: number of addressable units, number of blocks in main memory, number of lines in set, number of sets in cache, number of lines in cache, size of tag.

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter11: Operating Systems

Section: Chapter Questions

Problem 21VE

See similar textbooks

Similar questions

5. Suppose a byte-addressable computer using set-associate cache has 2^21 bytes of main memory and a cache of 64 blocks, where each cache block contains 16 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache; that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache; that is, what are the sizes of the tag, set, and offset fields?
Q: A digital computer has a memory unit of 64k * 16 and a cache memory of 1k words. The cache uses direct mapping with a block size of 4 words. i) How many bits are there in the tag, index, block & words fields of the address formats.ii) How many bits are there in each word of cache? iii) How many blocks can the cache accommodate? Note: this question is related from computer architecture subject kindly solved this correctly and completly.
Computer Science Consider a direct-mapped cache with 8 lines, each holding 16 bytes of data. The cache is byte-addressable and the main memory consists of 64 KB, which is also byte-addressable. Assume that a program reads 16KB of memory sequentially. Answer the following questions:a) How many bits are required for the tag, index, and offset fields of a cache address?b) What is the cache size in bytes?c) What is the block size in bytes?d) What is the total number of blocks in main memory?e) How many cache hits and misses will occur for the program, assuming that the cache is initially empty?f) What is the hit ratio?g) Give an example virtual address (in BINARY) that will be placed in cache line 5.
Q1. For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. Tag 31-10 Index 9-5 a) How many words of data in each cache line? b) How many lines does the cache have? c) d) Offset 4-0 What is the cache data size (in bits)? What is the ratio between total bits required for such a cache implementation over the data storage bits?
A computer of 32 bits has a cache memory of 64 KB with a cache line size of 64 bytes. The cache access time is 20 ns, and the miss penalty is 120 ns. The cache is 2-way associative. a) What is the number of cache lines? b) What is the number of cache sets? c) What is the number of lines per set? d) Draw a scheme of this cache. e) Calculate the time to read a word in case of miss.
Consider the following parameters: Parameter q) Width of the data bus Parameter r) Transfer time from Main Memory to Cache Parameter s) Transfer time from Cache to CPU Parameter t) Cache size Parameter u) Block size Which choice below best identifies the parameters that impact the cache hit rate: Parameters q) and r) only Parameters q) and t) only Parameters q), t), and u) only Parameter r), s), and t) only Parameters t), and u) only all of the above none of the above
A direct-mapped cache consists of 16 blocks. A byte-addressable main memory contains 4K blocks of 16 bytes each. Access time for the cache is 30 ns and the time required to fill a cache slot from main memory is 250 ns. Assume a request is always started in sequential to cache and then to main memory. If a block is missing from cache, the entire block is brought into the cache and the access is restarted. Initially, the cache is empty. a) Show the main memory address format that allows us to map addresses from main memory to cache. Be sure to include the fields as well as their sizes. b) Compute the hit ratio for a program that loops 4 times from locations 0 to 42 (base 10) in memory. c) Compute the effective access time for this program.
For a direct-mapped cache design with 64-bit addresses, the following bits of the address are used to access the cache: Tag Index Offset 63-13 12-4 3-0 a. What is the cache block size (in bytes)?b. What is the cache size (in bytes)?c. What is the total number of bits (including valid bit, tag bits and data array bits) to implement this cache?d. For the same block and cache sizes, you want to implement a 4-way set-associative cache, what is the number of index bit and the number of tag bits?
A direct-mapped cache consists of 8 blocks. A byte-addressable main memory contains 4K blocks of eight bytes each. Access time for the cache is 20 ns and the time required to fill a cache slot from main memory is 300 ns. Assume a request is always started in sequential to cache and then to main memory. If a block is missing from cache, the entire block is brought into the cache and the access is restarted. Initially, the cache is empty. c) Compute the effective access time for this program. Show me how to solve using this equation: EAT = H x AccessC + (1 – H) x AccessMM where H is the cache hit rate and AccessC and AccessMM are the access times for cache and main memory, respectively. thanks
8. Assume a certain system has an 8-bit address bus. After the system is powered on, the following byte-addressed cache references are recorded. Address Block 0 1 0 2 a) Fill in the table below to show the block address of each byte address reference. 3 4 0 4 3 16 V Tag V Tag 17 23 16 Address Block Address b) Assume the cache is a direct-mapped cache as shown below. 3 5 21 Data (4 bytes) Data (4 bytes) 17 23 V Tag Data (4 bytes) V Tag Data (4 bytes) 5 21 Fill in the table below to show the outcome of each address reference. Assume the cac is empty at the beginning. Note each data block has 4 bytes.
6. For a direct mapped cache comprising 16 single word blocks answer the following questions. Assume address and word sizes are both 32 bits and that the memory is byte addressed (4 bytes per 32-bit word). Enter answers as numbers only. How many index bits are there? How many offset bits are there? How many tag bits are there?
2. Suppose a computer using direct-mapped cache has 232 bytes of byte-addressable main memory and a cache of 1024 blocks, where each cache block contains 32 bytes. a) How many blocks of main memory are there? b) what is the format of a memory address as seen by the cache; that is, what are the sizes of the tag, block, and offset fields? c) To which cache block will the memory adress 0x000063FA map?