Computer Systems: A Programmer's Perspective (3rd Edition)
Computer Systems: A Programmer's Perspective (3rd Edition)
3rd Edition
ISBN: 9780134092669
Author: Bryant, Randal E. Bryant, David R. O'Hallaron, David R., Randal E.; O'Hallaron, Bryant/O'hallaron
Publisher: PEARSON
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Chapter 9.6, Problem 9.4PP

A.

Program Plan Intro

Virtual address:

Virtual page number (VPN) and virtual page offset (VPO) are the two components of virtual address. Virtual address is “14 bits” format.

B.

Program Plan Intro

The page size (P) is 64bytes; using the page size find the number of bits in VPN.

The formula for page size as follows:

P=2p

Substitute “P = 64” in the above formula

P=2p64=2p26=2pp=6

Therefore, the “p” value represents virtual page offset (VPO) and physical page offset (PPO).

Number of bits in VPN is calculated as follows:

n = 14

p = 6

NumberofbitsinVPN=np=146=8

The VPN has additional two more components. They are TLB tag (TLBT) and TLB index (TLBI). The TLB is “4 ways” associative with “16” entries totally. Using the TLB find the value of TLBI and TLBT.

The formula for TLB as follows:

T=2t

Substitute “T = 4” in the above formula

T=2t4=2t22=2tt=2

Therefore, the “t” value represents TLBI.

TLBI and TLBT are calculated as follows:

The “t” value represents TLBI. Therefore, the value of TLBI is “2”.

TLBI = 2

VPN = 8

TLBT=VPNTLBI=82=6

Therefore, the value of TLBT is “6”.

C.

Program Plan Intro

Physical address:

Physical page number (PPN) and physical page offset (PPO) are the two components of physical address. Physical address is “12 bits” format. The physical page offset (PPO) is identical to the virtual page offset (VPO).

D.

Program Plan Intro

The physical address has additional three more components. They are Byte offset within cache block (CO), Cache index (CI) and Cache tag (CT).

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Problem 2. The following table gives the parameters for a number of different caches. For each cache, fill in the missing fields in the table. Recall that m is the number of physical address bits, C is the cache size (number of data bytes), B is the block size in bytes, E is the associativity, S is the number of cache sets, t is the number of tag bits, s is the number of set index bits, and b is the number of block offset bits. Cache m C BES tsb 1 32 2048 256 2183 2372 2 32 4 4 3 32 1,024 8 64 256 4 |32|1,024|32|2| 16 5
Question 3 (Cache Memory Mapping): I (a) For the main memory address 0:0:0, briefly explain how a search is performed in two-way set associative mapping. Assume that the main memory size is 4 GB, the cache memory is 8 KB and the size of cache block is 32 bytes. (b) A 4-way set associative mapped cache consists of 64 blocks, divided into 4 sets. Main memory consists of 4K blocks, each containing 128 locations. Complete the following format for the main memory address by showing all your workings and find the tag size. [Hint: Calculate the no. of locations in the main memory, which gives the memory size in terms of the total number of bits] , Set No. Block No. Location Within Block No. of bits
Please help with a, b, and c:  Consider a virtual memory system that uses paging and a translation lookaside buffer (TLB) to cache the most recent virtual page-to-physical page translations. The following assumptions are made: The memory is byte addressable. Memory accesses are to 4-byte words. Virtual addresses are 20 bits wide. Physical addresses are 16 bits wide. The page size is 4096 bytes. The TLB is 4-way set associative with 16 total entries. The contents of the TLB and the page table for the first 32 pages are shown in the figure below:   TLB   Page Table Index Tag PPN Valid   VPN PPN Valid VPN PPN Valid 0 03 B 1   00 7 1 10 6 0   07 6 0   01 8 0 11 7 0   28 3 1   02 9 1 12 8 0   01 F 0   03 A 1 13 3 0 1 31 0 1   04 6 0 14 D 0   12 3 0   05 3 0 15 B 0   07 E 1   06 1 0 16 9 0…
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