Computer Systems: A Programmer's Perspective (3rd Edition)
3rd Edition
ISBN: 9780134092669
Author: Bryant, Randal E. Bryant, David R. O'Hallaron, David R., Randal E.; O'Hallaron, Bryant/O'hallaron
Publisher: PEARSON
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Chapter 6, Problem 6.42HW
Program Plan Intro
Given Information:
The given code is:
//declaration of buffer
char *cptr= (char *) buffer;
/* increment buffer pointer by iterating through buffer */
for(; cptr<((char*)buffer)+ 640*480*4; cptr++)
//reassign the value of cptr as "0"
*cptr=0;
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Check out a sample textbook solutionStudents have asked these similar questions
For the same 60 word fully associative cache with 30-word blocks,
say the LRU replacement algorithm is used, and the LRU is always kept in index 0.
And say you access the following 3 words, in the given order:
100, 120, 105
a) On the second access (the access of word 120),
in which index will the block containing 120 be placed?
Find out whether a certain cache is inclusive or exclusive by looking at the contents of it.
In this chapter, you will learn about the four cache replacement policies that have been discussed.
Chapter 6 Solutions
Computer Systems: A Programmer's Perspective (3rd Edition)
Ch. 6.1 - Prob. 6.1PPCh. 6.1 - Prob. 6.2PPCh. 6.1 - Prob. 6.3PPCh. 6.1 - Prob. 6.4PPCh. 6.1 - Prob. 6.5PPCh. 6.1 - Prob. 6.6PPCh. 6.2 - Prob. 6.7PPCh. 6.2 - Prob. 6.8PPCh. 6.4 - Prob. 6.9PPCh. 6.4 - Prob. 6.10PP
Ch. 6.4 - Prob. 6.11PPCh. 6.4 - Prob. 6.12PPCh. 6.4 - Prob. 6.13PPCh. 6.4 - Prob. 6.14PPCh. 6.4 - Prob. 6.15PPCh. 6.4 - Prob. 6.16PPCh. 6.5 - Prob. 6.17PPCh. 6.5 - Prob. 6.18PPCh. 6.5 - Prob. 6.19PPCh. 6.5 - Prob. 6.20PPCh. 6.6 - Prob. 6.21PPCh. 6 - Prob. 6.22HWCh. 6 - Prob. 6.23HWCh. 6 - Suppose that a 2 MB file consisting of 512-byte...Ch. 6 - The following table gives the parameters for a...Ch. 6 - The following table gives the parameters for a...Ch. 6 - Prob. 6.27HWCh. 6 - This problem concerns the cache in Practice...Ch. 6 - Suppose we have a system with the following...Ch. 6 - Suppose we have a system with following...Ch. 6 - Suppose that a program using the cache in Problem...Ch. 6 - Repeat Problem 6.31 for memory address0x16E8 A....Ch. 6 - Prob. 6.33HWCh. 6 - Prob. 6.34HWCh. 6 - Prob. 6.35HWCh. 6 - Prob. 6.36HWCh. 6 - Prob. 6.37HWCh. 6 - Prob. 6.38HWCh. 6 - Prob. 6.39HWCh. 6 - Given the assumptions in Problem 6.38, determine...Ch. 6 - You are writing a new 3D game that you hope will...Ch. 6 - Prob. 6.42HWCh. 6 - Prob. 6.43HWCh. 6 - Prob. 6.45HWCh. 6 - Prob. 6.46HW
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- Consider a fully-associative cache of size 4. Each slot in the cache can have just one item (i.e. the line size is 1 item). The cache is empty to start with. The cache uses an LRU replacement policy: every slot has a counter; every time a slot is accessed, a global counter is incremented and the value is stored in the slot counter; the slot with the lowest counter value is chosen for replacement. Sequence Id 1 2 3 4 5 6 7 8 10 Address Ox0012 0x0014 Ox0016 Ox0018 0x0016 0x0012 0x0020 Ox0022 0x0014 Ox0012 Hit/Miss Accesses 1 to 10 are respectively: Select one: O a. Miss, Miss, Miss, Miss, Hit, Hit, Miss, Miss, Miss, Miss O b. Miss, Miss, Miss, Miss, Hit, Hit, Miss, Miss, Hit, Hit O. Miss, Miss, Miss, Miss, Hit, Hit, Miss, Miss, Hit, Miss O d. Miss, Miss, Miss, Miss, Hit, Miss, Miss, Miss, Miss, Hit O e. Miss, Miss, Miss, Miss, Hit, Hit, Miss, Miss, Miss, Hitarrow_forwardA two-level cache hierarchy of L1 and L2 with 2 and 3 blocks respectively is designed. Both L1 and L2 are fully-associative with LRU replacement policy. A sequence of references (block addresses from left to right, denoted as letters) is given in the table. Both caches are empty initially. You need to simulate the contents of L1 and L2 for the given sequence. Note that each request goes to L1 first. A request is issued to L2 only if it misses L1. In case of a L2 hit, the requested block is fetched from L2 and placed into L1, both in the MRU position. In case of a L2 miss, the block is loaded from memory into both L1 and L2 caches in the MRU position. The cache contents are displayed by the block addresses from MRU position to LRU position, separated by a comma.arrow_forwardSuppose you are asked to have AMAT to be <=2 cycles. You have twolevels of cache. L1 Hit Time is 1 cycle and L2 Hit Time is 3 cycles; L2 Miss Rate 8% andL2 Miss Penalty is 150 cycles. What must you optimize your L1 miss rate to be? Showyour work.arrow_forward
- Given that a 4-way set associative cache memory has 64 KB data and each block contains 32 bytes. The main memory capacity is 4 GB. a. Find the number of bits for the main memory address. ANSWER: bits b. How many blocks are there in a set? ANSWER: blocks c. How many sets the cache has? ANSWER: d. The main memory address format is => | Tag: e. Which set will be mapped by the main memory address 458195h. ANSWER: sets bits | Set: bits | Word: bits | (in decimal)arrow_forwardThis chapter explains how to implement the four cache replacement policies.arrow_forwardAssume a direct-mapped cache that holds 4096 bytes, in which each block is 16 bytes.Assuming that an address is 32 bits and that cache is initially empty:a. Complete the table that follows. (You should use hexadecimal numbers for allanswers).b. Which, if any, of the addresses will cause a collision (forcing the block that was justbrought in to be overwritten) if they are accessed one right after the other? Explainarrow_forward
- In Figure 4.5, a flowchart of cache read operation is performed. Can you draw a cache write operation?arrow_forwardConsider the difference between a cache that is totally associative and one that is directly mapped.arrow_forwardHow does the cache know whether it contains a copy of the word at address A?arrow_forward
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