Write an ALP to exchange block of data word by word (8 words) between two memory locations. Assume memory1 address is 6000h and memory2 address is 7000h
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Write an ALP to exchange block of data word by word (8 words) between
two memory locations. Assume memory1 address is 6000h and memory2
address is 7000h
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- In a certain computer, the virtual addresses are 32 bits long and the physical addresses are 48 bits long. The memory is word addressable. The page size is 16 kB and the word size is 2 bytes. The Translation Look-aside Buffer (TLB) in the address translation path has 64 valid entries. Hit ratio of TLB is 100% then maximum number of distinct virtual addresses that can be translated is K.Suppose a computer using fully associative cache has 224 words of main memory and a cache of 512 blocks, where each cache block contains 16 words. How many blocks of main memory are there? What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag and offset fields? To which cache block will the memory reference 17042416 map?Suppose a computer using fully associative cache has 216 bytes of byte-addressable main memory and a cache of 64 blocks, where each cache block contains 32 bytes.Q.) What is the format of a memory address as seen by the cache; that is, what are the sizes of the tag and offset fields?
- Suppose a computer using set associative cache has 216 words of main memory and a cache of 128 blocks, and each cache block contains 8 words. If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields?Suppose a virtual memory address is 0x123456789012. Divide this address into the 4 different page table parts and the within page offset.What advantages do segmented memory address translation provide over a straight translation?
- Suppose a specific MCU has the following size of memories: 2 M byte of flash, starting from 0x0800_0000, 256 k byte of SRAM starting from 0x2000_0000, and 8 k byte registers for GPIOs, start at 0x4001_0000. (Note that 0x is the prefix for hexadecimal numbers.) Draw the memory map based on your calculations for the addresses.Suppose a computer using direct mapped cache has 2^32 bytes of byte-addressable main memory and a cache size of 512 bytes, and each cache block contains 64 bytes. a. How many blocks of main memory are there? b. What is the format of a memory address as seen by cache, i.e., what are the sizes of the tag, block, and offset fields?Suppose a computer using fully associative cache has 224 words of main memory and a cache of 128 blocks, where each cache block contains 16 words. a. How many blocks of main memory are there? b. What is the format of a memory address as seen by the cache, that is, what are the sizes of the tag and word fields? c. To which cache block will the memory reference 01D87216 map?
- Write a service routine which resets all elements of an array that resides in memory location from A000 H to A0FF H with DS equal to 0000 H. The service routine address is CS:IP where CS is 2000 H and IP is 0100H. Assume the interrupt type that is called is 50 (x8086- nano)Suppose a computer using fully associative cache has 224224 words of main memory and a cache of 512 blocks, where each cache block contains 16 words. a. How many blocks of main memory are there? b. What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag and offset fields? c. To which cache block will the memory reference 1604181616041816 map? Also... Suppose a computer using set associative cache has 216216 words of main memory and a cache of 128 blocks, and each cache block contains 8 words. a. If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b. If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?What are the advantages of segmented memory address translation over straight translation?