Suppose we have a processor with a base CPI of 1.2, assuming all references hit in the primary cache, and a clock rate of 3.5 GHz. Assume a main memory access time of 120 ns, including all the miss handling. Suppose the miss rate per instruction at the primary cache is 4%. How much faster will the processor be if we add a secondary cache that has a 7-ns access time for either a hit or a miss and is large enough to reduce the miss rate to main memory to 0.3%?

Suppose we have a processor with a base CPI of 1.2, assuming all references hit in the primary cache, and a clock rate of 3.5 GHz. Assume a main memory access time of 120 ns, including all the miss handling. Suppose the miss rate per instruction at the primary cache is 4%. How much faster will the processor be if we add a secondary cache that has a 7-ns access time for either a hit or a miss and is large enough to reduce the miss rate to main memory to 0.3%?

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

See similar textbooks

Similar questions

Suppose we have a processor with a base CPI of 2.0 assuming all references hit in the pnmary cache and a clock rate of 1000 MHz. The main memory access time is 100 ns. Suppose the miss rate per instruction is 5%. What is the revised CPI? How much taster will the machine run it we put a secondary cache (with 20-ns access time) that reduces the miss rate to memory to 2%
Suppose we have a processor with a base CPI of 1, assuming all references hit in the primary cache, and a clock rate of 2 GHz. Assume a main memory access time of 200 ns, including all miss handling. Suppose the miss rate per instruction at the primary cache is 3%. How much faster will the processor be if we add a secondary cache that has 10 ns access time for either a hit or a miss and is large enough to reduce the miss rate to main memory to 1%?
Asap
A cache memory has a line size of eight 64-bit words and a capacity of 4K words. The main memory size that is cacheable is 1024 Mbits. Assuming 4-way set associative mapping and that the addressing is done at the byte level. What is the format of the main memory addresses (i.e s-d, d, and w)? For the hexadecimal main memory location 2BFACEDH, find the corresponding 4-way set-associative memory format
Suppose you have a processor with a base CPI 1.0, assuming all references hit in theprimary cache (L1), and a clock rate of 3 GHz. Assume that you have two caches (L1and L2). L2 cache access time is 10 ns and main memory access time is 200 ns,including all the miss handling. Suppose the miss rate per instruction at the L1 cache is10%, L2 cache is 5%.a) What is the effective CPI?b) What will be the effective CPI if we add a new cache (L3) that has 50 nsaccess time and reduce the miss rate to main memory to 1%?
Suppose cache has a hit rate of 0.89 and access time of 5ns, main memory has a hit rate of 0.98 and access time of 60ns, and virtual memory has an access time of 700 us (microseconds). What is the average memory access time in us?
Consider a CPU with clock cycle of 10ns that executes program A in 100 clock cycles and access the memory for 50 times during the execution. The CPU uses the cache with miss rate of 7% and Miss Penalty time of 40 ns. Compare the CPU execution time with and without Cache miss
Assume the miss rate of an instruction cache is 2% and the miss rate of the data cache is 4%. If a processor has a CPI of 2 without any memory stalls and the miss penalty is 100 cycles for all misses, determine how much faster a processor would run with a perfect cache that never missed. Assume the frequency of all loads and stores is 36%.
Suppose a byte-addressable computer using set associative cache has 8M byes of main memory and a cache of 128 blocks, where each cache block contains 64 bytes. a) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 16-way set associative, what is the format of a memory address as seen by the cache
Suppose a byte-addressable computer using set associative cache has 2^24 bytes of main memory and a cache size of 64K bytes, and each cache block contains 32 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?
A CPU has 32-bit memory address and a 256 KB cache memory. The cache is organized as a 4-way set associative cache with cache block size of 16 bytes. a. What is the number of sets in the cache? b. What is the size (in bits) of the tag field per cache block? c. What is the number and size of comparators required for tag matching? d. How many address bits are required to find the byte offset within a cache block? e. What is the total amount of extra memory (in bytes) required for the tag bits?
Suppose a byte-addressable computer using set associative cache has 4Mbyes of main memory and a cache of 64 blocks, where each cache block contains 8 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache? Show all work and explain how you got the answers please. Thanks