Q: For a basic computer that is currently running in its timing TO of execution for an instruction that is located in memory location 366. The content of AC is (212) and the content of memory locations are as follow: [memory location: content]: [365:9473], [366:7010], [367:5431], [368:4620], [431:1A23], [620:C80D]. Answer the following questions that examine the contents of PC, AR, AC, DR and IR after the end of execution for the next instruction. (Note: all numbers are in
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- _____ is a CPU design technique in which instruction execution is divided into multiple stages and different instructions can execute in different stages simultaneously.E In the following code block(Reference:Q11), you will a set of assembly instructions with corresponding line numbers (line numbers are for informational purpose only and they are not part of the source code). 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 mov edx, 5 dec ecx jmp LABEL1 mov eax, 1 LABEL1: mul edx jmp ecx mov edx, 0678h sub edx, eax jmp DWORD PTR [edx] neg ebx add ecx, ebx mov eax, 0 For each of the conditions/scenario listed below, indicate the corresponding line number (that cause or is associated with the condition/scenario). Enter 0 (Zero) if the condition is not caused by the block of code. 1) Memory indirect jump: type your answer... type your answer... type your answer... type your answer... 2) Register indirect jump: 3) Relative short jump: type your answer... 5) Two's complement type your answer... 4) Relative near jump: 6) Unreachable codeQuestion Q: For a basic computer that is currently running in its timing TO of execution for an instruction that is located in memory location 366. The content of AC is (212) and the content of memory locations are as follow: [memory location: content]: [365:9473], [366:7010], [367:5431], [368:4620], [431:1A23], [620:C80D]. Answer the following questions that examine the contents of PC, AR, AC, DR and IR after the end of execution for the next instruction. (Note: all numbers are in Hexadecimal.) p 4:33 The content of AC after the end of * :execution for the next instruction is 700 O 620 320 O None of the choices O 4:35 /
- Computer Science A[10] = x; Let x is saved in the register ($s0) and the base address of array A is saved in register ($s3). What is the equivalent MIPS instruction of this high-level language?Question Q: For a basic computer that is currently running in its timing TO of execution for an instruction that is located in memory location 366. The content of AC is (212) and the content of memory locations are as follow: [memory location: content]: [365:9473], [366:7010], [367:5431], [368:4620], [431:1A23], [620:C80D]. Answer the following questions that examine the contents of PC, AR, AC, DR and IR after the end of execution for the next instruction. (.(Note: all numbers are in Hexadecimal The content of IR after the end of execution :for the next instruction is 4620 O 9473 5431 None of the choices 7010 OSingle instruction computer (SIC) has only one instruction that for all operations our MIPS does. The instruction has the following format. sbn a, b, c # Mems[a]=Mem[a]- Mem[b]; if (Mem[a]<0) go to PC+c For example, here is the program to copy a number from location a to location b: Start: sbn temp, temp, 1 sbn temp, a, 1 sbn b, b, 1 sbn b, temp, 1 So build SIC program to add a and b, leaving the result in a and leaving b unmodified.
- Problem 1. This problem is about operand modes, in particular about memory addressing using the operand modes described in lecture and the textbook. The following shows the contents of a portion of the program memory (locations Ox10000 through 0x10040), and certain registers. All contents are 64-bit quantities. Address Memory Contents 0x10040 0x10038 0x10030 0x10028 0x10020 0x10018 0x10010 0x10008 0x10000 a. movq (%rdi), %rax b. movq (%rdi,%rsi), %rax 100 0x10040 200 25 0x10028 0x10020 c. movq 8(%rdi, %rcx, 4) %r8 d. movq -8(%rdi,%rsi), rbx 500 0x10018 2 Register Contents %rdi 0x10008 %rsi %rdx %rcx For each of the following instructions, say what value ends up in the destination register. Each instruction starts with the state shown above, i.e., the effects do not accumulate. 0x20 8 4The Problem Using C programming language write a program that simulates a variant of the Tiny Machine Architecture. In this implementation memory (RAM) is split into Instruction Memory (IM) and Data Memory (DM). Your code must implement the basic instruction set architecture (ISA) of the Tiny Machine Architecture: 1 LOAD 2→ ADD 3→ STORE 4 → SUB 5> IN 6> OUT 7> END 8 → JMP 9> SKIPZ Each piece of the architecture must be accurately represented in your code (Instruction Register, Program Counter, Memory Address Registers, Instruction Memory, Data Memory, Memory Data Registers, and Accumulator). Data Memory will be represented by an integer array. Your Program Counter will begin pointing to the first instruction of the program. For the sake of simplicity Instruction Memory (IM) and Data Memory (DM) may be implemented as separate arrays. Hint: Implementing a struct for your Instructions and an array of these structs as your Instruction Memory greatly simplifies this program. Example:…Q2/ The following program have been executed by an 8085 Microprocessor. Write down the sequence of the process with explain of each step. Address (Hex) 8085 Instruction 5011 LXI B, 11FF 5013 DCX B 5014 MVI B, 00 5015 DCR B 5016 MVI H, A1 5018 INR H
- . A digital computer has a memory unit with 32 bits per word. The instruction set consists of 147 different operations. All instructions have an operation code part (opcode) and two address fields: one for a memory address and one for a register address. This particular system includes eight general-purpose, user-addressable registers. Registers may be loaded directly from memory, and memory may be updated directly from the registers. Direct memory-to-memory data movement operations are not supported. Each instruction stored in one word of memory. a) How many bits are needed for the opcode? b) How many bits are needed to specify the register? c) How many bits are left for the memory address part of the instruction? d) What is the maximum allowable size for memory? e) What is the largest unsigned binary number that can be accommodated in one word of memory?Using C programming language write a program that simulates a variant of the Tiny MachineArchitecture. In this implementation memory (RAM) is split into Instruction Memory (IM) and DataMemory (DM). Your code must implement the basic instruction set architecture (ISA) of the TinyMachine Architecture:1 -> LOAD2 -> ADD3 -> STORE4 -> SUB5 -> IN6 -> OUT7 -> END8 -> JMP9 -> SKIPZEach piece of the architecture must be accurately represented in your code (Instruction Register, ProgramCounter, Memory Address Registers, Instruction Memory, Data Memory, Memory Data Registers, andAccumulator). Data Memory will be represented by an integer array. Your Program Counter will beginpointing to the first instruction of the program. Input SpecificationsYour simulator must run from the command line with a single input file as a parameter to main. This filewill contain a sequence of instructions for your simulator to store in “Instruction Memory” and then runvia the…For the assembly language program and memory map given below, Assembly LOADI RO, -1 Memory Loc Machine Code 00101111 LOADI R1, -3 1 00111101 ADD RO, RO ADDI R1, 2 ADDI RO, 3 SRO RO, R1 ADD R1, RO 7 01000010 3 01110010 01100011 10001100 4 01010010 10000010 SRO RO, RO Trace the program execution for 4 Fetch/Decode/Execute cycles. Enter the register contents in the spaces provided. Assume all registers are initialized to zeros at the start of the execution. Further, assume that execution starts at memory location 0. Note: ALL answers must be given in BINARY not decimal form. RO: R1: PC: IR: OUT: IN: