Problem: Assume that all memory access operations are completed in one clock cycle in a processor that has a 1-GHz clock. What is the frequency of memory access operations if Load and Store instructions constitute 20 percent of the dynamic instruction count in a program? (The dynamic count is the number of instruction executions, including the effect of program loops, which may cause some instructions to be executed more than once.) Assume that all instructions are executed in 5 clock cycles.

Problem: Assume that all memory access operations are completed in one clock cycle in a processor that has a 1-GHz clock. What is the frequency of memory access operations if Load and Store instructions constitute 20 percent of the dynamic instruction count in a program? (The dynamic count is the number of instruction executions, including the effect of program loops, which may cause some instructions to be executed more than once.) Assume that all instructions are executed in 5 clock cycles.

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

See similar textbooks

Similar questions

Assignment-04. A non-pipelined CPU has 12 general purpose registers (RO, R1, R2, . Following operation are supported: R12), .... ADD Ra, Rb, Rr Add Ra to Rb and store the result in Rr MUL Ra, Rb, Rr Multiply Ra to Rb and store the result in Rr MUL operations takes two dlock cycles, ADD takes one clock cycle. Calculate minimum number of clock cycles required to compute the value of the expression XY +XYZ + YZ The variables X,Y, Z are initially available in registers RO, R1 and R2 and contents of these registers must not be modified,
Rearrange the following code to minimize the total number of cycles, assuming that a dependent instruction following the load will need two clock cycles of delay before getting the data. Load r1, 64 (r2)Add r2, r2, r2Sub r3, r4, r1Load r4, 32 (r4)
Assume for a given program, 60% of the executed instructionsare of Class A, 10% are of Class B, and 30% are of Class C. Furthermore,assume that an instruction in Class A requires 3 cycles, an instruction inClass B requires 2 cycles, and an instruction in Class C requires 2 tocomplete. i. Compute the overall CPI for this program.ii. Compute the clock rate of the CPU when the time it takes tocomplete 20 instructions is 1.73 ???????????
Problem 1: Working with MARIE Write MARIE code to perform the following pseudocode excerpt, with an explanation of each instruction in your code beside it. Input a value for x if(x > y) max= x else max=y Output the value of max Provide a screenshot of the simulation result (A screenshot of the MARIE Simulator window after running the program, showing the value at the output window). Instructions: Use “ORG” instruction to start your program at an address equivalent to 102410. Use your last university ID number to input the new value of x. For example, if your ID is 2315161678235, then you will use the number 5 as the value of x (value of y will be used as assigned below) Do not forget to change the Input and output boxes to decimal! You should include the necessary labels and directives at the end of your program: X, Dec 0 And, Dec 6 max, Dec 0
Problem 1. This problem is about operand modes, in particular about memory addressing using the operand modes described in lecture and the textbook. The following shows the contents of a portion of the program memory (locations Ox10000 through 0x10040), and certain registers. All contents are 64-bit quantities. Address Memory Contents 0x10040 0x10038 0x10030 0x10028 0x10020 0x10018 0x10010 0x10008 0x10000 a. movq (%rdi), %rax b. movq (%rdi,%rsi), %rax 100 0x10040 200 25 0x10028 0x10020 c. movq 8(%rdi, %rcx, 4) %r8 d. movq -8(%rdi,%rsi), rbx 500 0x10018 2 Register Contents %rdi 0x10008 %rsi %rdx %rcx For each of the following instructions, say what value ends up in the destination register. Each instruction starts with the state shown above, i.e., the effects do not accumulate. 0x20 8 4
1. When a program is adapted to run on multiple cores in a multiprocessor system, the execution time on each core is comprised of computing time and the overhead time required for locked critical sections and/or to send data from one core to another. Assume a program requires t = 200 sec of execution time on one core. When run on n cores, each core requires t/n sec, as well as an additional 10 sec of overhead, irrespective of the number of cores. a. Compute the per-core execution time for 2, 4, 8, 16, 32, 64, and 128 cores. b. For each case, list the corresponding speedup relative to a single core and the ratio between actual speedup versus ideal speedup (speedup if there was no overhead).
Computers Problem 3. Suppose you wish to run a program P with 7.5 billion instructions on a 5GHZ machine with a CPI of 0.8. What is the expected CPU time? When you run P, it takes 3 seconds of wall clock time to complete. What is the percentage of CPU time P recelved?
5. Below is a depiction of a loop in instruction memory address Охо TOP: instruction 1 Ox4 instruction 2 Ox8 instruction 3 OxC instruction 4 Ох10 conditional branch to TOP Assume that the branch target buffer is initially empty, and the prediction bits are set to Strongly Taken (ST). Fill in the blanks On the first pass through the loop we take the branch. The branch target bits are now We suffer stalls. On the second pass through the loop we don't take the branch. The branch target bits are now We suffer stalls. On the third pass through the loop we don't take the branch. The branch target bits are now We suffer stalls. On the fourth pass through the loop we don't take the branch. The branch target bits are now We suffer stalls.
18 What is speculation as it relates to parallelization? It is the set of instructions that issues together in one clock cycle and the packet may be determined statically by the compiler or dynamically by the processor. It is a style of instruction set architecture that launches many operations that are defined to be independent in a single wide instruction, typically with many separate opcode fields. It is the number of clock cycles between a load instruction and an instruction that can use the result of the load without stalling the pipeline. O It is an approach whereby the compiler or processor guesses the outcome of an instruction to remove it as a dependence in executing other instructions.
For the same instruction being executed: add $s1, $s2, $t0 using the following delays for each block/action: Decode + Register File Read Data Memory Access Instruction Register Read ALU (all Register Mux Memory Access operations) Write 25 200 |125 150 300 25 10 But, now assume that all types of instructions have to be executed in one clock cycle, not just the 'add' instruction. What is the minimum clock cycle from the times below which will suffice as the clock cycle time to run the microprocessor at? Choose the best answer. 845 535 545 835
Assume that the operation times of one add instruction for the major functional units are 325 ps for memory access, 185 ps for ALU operations and 125 ps for register file read/writes. Please fill the table first and perform the following a )What is the total cycle in single-cycle implementation? b )What is the total cycle in pipelining implementation? c) What is the total cycle in pipelining implementation if there are 5 million add instructions? d) What is the total cycle in pipelining implementation for 5 million add instructions, if the stages are balanced? e)What is the speed up of pipelining implementation over single-cycle implementation?
Assume accessing the memory would take 1000 ns and accessing the registers would take 1 ns. Compute the total time execution of the following assembly code snippets. Show the execution time of each instruction. You can only focus on the time of data access and ignore the CPU cycles. [Hints: the key to answer this question is to tell whether each line of instruction is accessing the memory or not.] Code Snippet #1: Mov EAX,[0x00089871] Mov EBX, 0 ADD EAX, EBX XOR EAX, EAX Code Snippet #2: Mov ECX, [0x00082712] Mov EAX, 9 Mov EBX, 0×000008FF SUB EAX, EBX ADD EAX, ECX LEA EDX, [0X0009004F] TEST EAX, EAX JNZ EDX