nas a TLB able entries minimum

Systems Architecture
7th Edition
ISBN:9781305080195
Author:Stephen D. Burd
Publisher:Stephen D. Burd
Chapter6: System Integration And Performance
Section: Chapter Questions
Problem 22VE
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A CPU generate a 64-bit virtual addresses. The
page size is 64KB. The processor has a TLB
which can hold a total of 2M-page table entries
and is 16 -way set associative. The minimum
size of the TLB tag is bits. (Assume that
system is byte addressable)
Transcribed Image Text:A CPU generate a 64-bit virtual addresses. The page size is 64KB. The processor has a TLB which can hold a total of 2M-page table entries and is 16 -way set associative. The minimum size of the TLB tag is bits. (Assume that system is byte addressable)
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