Given a MIPS processor with a direct-mapped data cache. On this processor the following code is running: sum = 0; for (i=0; i<4; i++) sum = sum + A) + A[i+2); 'A' is an array of (32-bit) integers, word-aligned in memory. All other variables used in this program are already located in registers. What is the data cache hit-rate (in number of percents) for this program, assuming that the cache has a block size of 1 word? Answer:
Given a MIPS processor with a direct-mapped data cache. On this processor the following code is running: sum = 0; for (i=0; i<4; i++) sum = sum + A) + A[i+2); 'A' is an array of (32-bit) integers, word-aligned in memory. All other variables used in this program are already located in registers. What is the data cache hit-rate (in number of percents) for this program, assuming that the cache has a block size of 1 word? Answer:
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![Given a MIPS processor with a direct-mapped data cache. On this processor the following code is running:
sum = 0;
for (i=0; i<4; i++)
sum = sum + A[i) + A[i+2];
'A' is an array of (32-bit) integers, word-aligned in memory. All other variables used in this program are already located in registers.
What is the data cache hit-rate (in number of percents) for this program, assuming that the cache has a block size of 1 word?
Answer:](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F68583ec6-9557-4c92-985e-8cdc66bd922d%2Fbfa7c2b0-c465-4d7a-87d1-27e863f45684%2Fda0tu6b_processed.jpeg&w=3840&q=75)
Transcribed Image Text:Given a MIPS processor with a direct-mapped data cache. On this processor the following code is running:
sum = 0;
for (i=0; i<4; i++)
sum = sum + A[i) + A[i+2];
'A' is an array of (32-bit) integers, word-aligned in memory. All other variables used in this program are already located in registers.
What is the data cache hit-rate (in number of percents) for this program, assuming that the cache has a block size of 1 word?
Answer:
Transcribed Image Text:A data cache is indexed with a 8-bits inciex, tag size is 24 bits. Each cache block contains a tag, a block of words, 1 dirty bit, 1 valid bit; each word contains 4 bytes. The address size is 36 bits, and the
memory is byte addressable.
8) The cache is drect mapped.
Compute for yourself how many words are stored in one data block.
a) What is the total cache size (in bits)? Write the total cache size into the arswer line (without decimal sign ".").
Answer:
A direct mapped cache has the fallowing metrics for a program execution:
D-cache miss rate = 5%
I-cache miss rate 4%
Miss penalty = 200 cycles
Base CPI (ideal cache) = 5.0
The D-cache misses are caused only by the Load and Store instructions. These instructions are only 20% of total amount of instructions.
Caiculate the actual CPI, then compute and write down how much faster is the ideal processor with 5.0 CPL.
Answer:
Consider a cache which is able to store 2048 bytes of memory data. To what cache block (entry) does the address 400 map, if this cache has 2-word blocks and is direct mapped?
Answer:
A direct mapped cache has the following metrics for a program execution:
D-cache miss rate = 4%
l-cache miss rate = 6%
Miss penalty = 200 cycles
Base CPI (ideal cache) = 4.0
The D-cache misses are caused only by the Load and Store instructions. These instructions are only 40% of total amount of instructions.
Calculate the actual CPI, then compute (and write down) how much faster is the ideal processor with 4.0 CPI.
(In yaur answer, use decimal point for nan-integer numbers).
Answer:
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