Consider the following set of Boolean functions W (p, q. r) = E(0,1, 6,7) X (p. q. r) (0,3.5,7) Y (p, q. 1) = E(2,4) (a) Deduce the optimal ROM truth table for the above functions. (b) Draw the ROM logic diagram to implement the circuit.
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- (a) Use Karnaugh map to simplify the function f(A,B,C,D)=Em(1,5,7,8,9,10,11,14,15) (b)Draw a logic circuit to implement the simplified expression.Q1: Let F1 = X.Ỹ, F2 = A OB, F3 = F1 + F2 Implement the above Boolean expression with logic circuit . giving the truth table. Q2: Construct digital circuit to add two numbers with 4 bit long.. Giving all steps ( with example ). Q3 : Convert the following to their equivalent :- 1- ( BBE )16 = ( ? ho 2- ( 15.73 ), = ( ? 2 %3D %3D 3- ( 11111100 )1's complement = ( ? Junsigned integer %3D 4- ( 2.57 )s + ( 527 )s = ( ? s 5- (111.1011 )2 = ( ? ho %3DConstruct a circuit diagram that checks whether the two numbers A and B are in the ratio of 2:3. Also, derive the final Boolean equation for the function. F = 1 if A: B = 2: 3,0 otherwise Here, A and B both are 3 bit binary numbers. NB: You cannot use the IC of comparator, meaning for the comparison part, you need to draw the gate level diagram. You can use block level diagrams for the rest of the parts.
- : Implement the following Boolean functions by using: PLA(Programming Logic Array).and design logic circuit f1(A,B,C,D)=E m(1,3,4,5,6,7,12,14). f2(A,B,C,D)=Em (1,3,4,6,9,11,12,14). f3(A,B,C,D)=Em (0,2,4,6,8,9,10,11,12,13,14,15). f4(A,B,C,D)=E m(0,1,2,3,4,5,7,8,9,10,11,13,15).B. Given f(a, b,c,d, e) = Em(0,1,6,10,12,14,16,17,26,30). Find the minimum cost logic circuit that implements the function f(a,b,c,d, e) using a 5-variable Karnaugh map simplification. a. Draw the logic circuit after simplification. b. Calculate the implementation cost.Design a 3-bit counter that counts the following sequence: 7,5, 3. 1.0.7, 5. 3, 1, 0, 7. etc. Using the sequential design technique that starts from a state diagram, draw the state table. minimize the logic. and draw the final circuit. The outputs of logic circuit are 2 = Qo Q1. I, = Qo.Qi + Qo.Qi, Io = Qo.Q2, Cont2 = Qj Q2 Cont1 = Qu Q2. Cont0 = Q2 Qo.Q1. h = Qo.Qi + Qo.Q1, Io = Qo Qz Cont2 = Q, Q2 Contl = Qo Q2 Cont0 = Q2 Qo Qı Ij = Qo.Q, + Q».Qı, Io = Qo. Q2. Cont2 = Qj Q2. Contl = Qo.Q2. Cont) = Q2 L = Qo.Qı. I¡ = Q. Qj + Qu Q Io = Qv.Qz Comt2 = Q, Q, Contl = Q Q2 Cont0 = Q2 !! fefsto How much will be per-product cost and th
- This question is from the subject Digital Logic Design. Q2. Two Boolean functions are represented in the following truth table.a) Represent the function F1 and F2 in Some of Min-terms (SOM).b) Simplify both functions as Some of Products (SOP).5- Implement a logic circuit to verify the following logic function: F= E 1,2,3,4,5,7,8,12,13|| The design work should include the followings: a. Derivation of the minimized Boolean expression in POS from the Karnaugh map. b. Implement a circuit by using NOR gates only.Design a circuit called half adder (HA) which adds two 1-bit numbers, a,b and produces 2-bit output, c. a. Draw the truth table of the circuit.b. Find the Boolean functions of each bit of the output.c. Optimize the Boolean functions.d. Draw the logic diagram of the optimized circuits.e. Write the VHDL code of the logic diagrams by using “Dataflow modeling” method f. Simulate the circuits that you have designed in 1.e. Prepare a simulation waveform for you report.g. Produce the RTL schematic for the circuit that you have designed in 1.e.
- Q 5. Determine the expression of the given logic circuit and simplify it. (using De'Morgan's law / Boolean rules) E- Using a 8 X 1 PROM, implement the logic function whose truth table is given : B. C Output (F) 0. 1. 1. 0. 1. 0. 1 0. 1. 1. 6761 Design a combinational logic circuit that accept (4-bit) binary number (A) and generate an output binary number (X), if you know that (X = 2's complement (A) ): a. Draw the system block diagram. b. List the truth table. c. List the algebraic expressions in SOP. d. List the algebraic expressions in POS. e. Draw the logic diagram.