Solve. 1.Consider a system with 2 level cache. Access times of Level 1, Level 2 cache and main memory are 0.5 ns, 5 ns and 100 ns respectively. The hit rates of Level1 and Level2 caches are 0.7 and 0.8 respectively. What is the average access time of the system ignoring the search time within cache ?

Solve. 1.Consider a system with 2 level cache. Access times of Level 1, Level 2 cache and main memory are 0.5 ns, 5 ns and 100 ns respectively. The hit rates of Level1 and Level2 caches are 0.7 and 0.8 respectively. What is the average access time of the system ignoring the search time within cache ?

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

See similar textbooks

Similar questions

Computer Science Consider a computation running on a machine with a 1 GHz clock, 8-word cache line, single cycle access to the cache, and 100 ns latency to DRAM. The computation has a cache hit ratio at 1 KB of 40% and at 32 KB of 70%. Consider three cases: (1) a single threaded execution without caches, (2) a single threaded execution in which the entire cache is available to the serial context, and (3) a multithreaded execution with 32 threads where each thread has a cache residency of 1 KB. Calculate the required bandwidths for all the three cases respectively.
Suppose we have a byte-addressable computer using fully associative mapping with 16-bit main memory addresses and 32 blocks of cache. Supposed also that each block contains 16 bytes. The size of the offset field is 19 bits and the size of the block field is 0.625 bytes.
Task 6. Consider a paging system with the one-level page table stored in memory. (a) If a memory reference takes 10 ns (nanoseconds), how long does a paged memory reference take? (b) If we add TLBS, and if 90 percent of all page-table references are found in the TLBS, what is the effective memory reference time? (Assume that finding a page-table entry in the TLBS takes 0.5 nanoseconds, if the entry is present.)
Suppose cache has a hit rate of 0.89 and access time of 5ns, main memory has a hit rate of 0.98 and access time of 60ns, and virtual memory has an access time of 700 us (microseconds). What is the average memory access time in us?
Suppose we have a byte-addressable computer using fully associative mapping with 16-bit main memory addresses and 32 blocks of cache. If each block contains 16 bytes: (a) Determine the size of the offset field. (b) Determine the size of the tag field.
Suppose a byte-addressable computer using set associative cache has 2^24 bytes of main memory and a cache size of 64K bytes, and each cache block contains 32 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?
On the Motorola 68020 microprocessor, a cache access takes two clock cycles. Data access from main memory over the bus to the processor takes three clock cycles in the case of no wait state insertion; the data are delivered to the processor in parallel with delivery to the cache. a. Calculate the effective length of a memory cycle given a hit ratio of 0.9 and a clocking rate of 16.67 MHz. b. Repeat the calculations assuming insertion of two wait states of one cycle each per memory cycle. What conclusion can you draw from the results?
Suppose a computer using fully associative cache has 224 bytes of byte-addressable main memory and a cache of 128 blocks, where each block contains 64 bytes.Q.) What is the format of a memory address as seen by cache; that is, what are the sizes of the tag and offset fields?
(b) Consider a paging system with the page table stored in memory. If a memory referencetakes 200 nano seconds, how long does a paged memory reference take? If we add a TLB,and 75% of all page references are found in the TLB, what is the effective memory referencetime? (Assume that it takes zero time to find an entry in the TLB if it is already present).
Assume the miss rate of an instruction cache is 4% and the miss rate of the data cache is 5%. If a processor has a CPI of 3 without any memory stalls, and the miss penalty is 50 cycles for all misses, determine how much faster a processor would run with a perfect cache that never missed. Assume the frequency of all loads and stores is 44%.
Suppose a computer using set associative cache has 216 words of main memory and a cache of 128 blocks, and each cache block contains 8 words. If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields?
Suppose a computer using direct mapped cache has 2^32 bytes of byte-addressable main memory and a cache size of 512 bytes, and each cache block contains 64 bytes. a. How many blocks of main memory are there? b. What is the format of a memory address as seen by cache, i.e., what are the sizes of the tag, block, and offset fields?