Based on the given information, find the process capability ratio cp ?
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Meena Chavan Corp.'s computer chip production process yields DRAM chips with an average life of 1600 hour and a sd=80 hours.The tolerance upper and lower specification limits are 2200 hours and 1500 hours, respectively.Based on the given information, find the process capability ratio cp ?
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- Consider a CPU manufacturing process using 300mm wafers. a. If the dimensions of the die are 1.2cm x 0.8cm, what is the approximate number of dies produced? b. Assuming a defect density of 0.55/cm?, what is the die yield?With drawing Compute the Average access time for memory system when the time for Main Memory is 2000 ns, the time for cache is 200 ns and hit ratio is 0.9?If the execution times using the base machine and the target machine are as follows, what is the SPEC ratio? Benchmark 1 Benchmark 2 Benchmark 3 Benchmark 4 Benchmark 5 Base Machine 1 sec 10 sec 100 sec 96 sec 800 sec Target Machine 0.5 sec 2.5 sec 12.5 sec 6 sec 25
- Suppose that the processor has access to two levels of memory. Level 1 contains 1000 data words and has an access time between the CPU and L1 of 2.5 nanoseconds (2.5E-9 sec); level 2 contains data 100,000 words and has an access time between L1 and L2 transfers of 5.0 nanoseconds (5.0E-9 sec). What is the average memory assess time in nanoseconds for data requests by the CPU?Two different computer processors are compared by measuring the processing speed fordifferent operations performed by computers using the two processors. Given that 12measurements with the first processor had a standard deviation of 0.1 GHz and 16measurements with the second processor had a standard deviation of 0.15 GHz. Can we say that the processing speed of the second processor is less uniform? Use a 0.05 level of significance. What assumptions should be made so as to show how the two samples are obtained?Ques 2: Consider the design of pipelined stages. Following are the specifications. Logic delay (T) = 100ns Logic gates (G) = 100 Latch delay (S) = 10ns Latch gates (L) = 10 Consider the design of a pipelined processor where the optimal number of stages are obtained by minimizing area and maximizing throughput. What is the maximum throughput (in MIPS) of the pipelined design?
- Soru 2 ns057008-98716112 Alternative-1 Alternative-2 Alternative-3 W1 =0,20 25 205057008 - 98716112 W2=0,40 y2050 In an MCDM problem there are three alternatives and three criteria. All of the three citeria are more is better criteria. Weights of each criteria are given as 15 20 10 30 W3=0,40 15 5 40 205057008 - 98716112 wl= 0.20, w2=0.40 and w3=0.40. Decision matrix is given above. Solve this problem by using ELECTRE method 20 y205057008 - 98716112 057008 - 98 y205057008 - 98716112 57008 - 987 20so57008 - 9871611203 A A>C,B C>B y205057008 - 98716112 y20505700371611203 .205057008 - 9871611203 B 57008 -9 A>C,B B>C A>B>C 57008-987 w205057008 - 9871611203 C>A,B A>B C>A>B y205057008- 9871611203 y205057008-9871611203 D 57008-987 C>A,B B>A C>B>A E y205057008 - 9871611203 p09871611203 57008 - 9871611203 B>C,A C>A B>C>A y205057008- 9871611203 y205057008- 9871611203 057008- 987 1611203 y205067008 - 9871611203 y205057008-9871611203 y205057008 - 9871611203 y205057008 - 9871611203 1203 y205057008-…The Pentium 4 Prescott processor, released in 2004, had a clock rate of 3.6 GHz and voltage of 1.25 V. Assume that, on average, it consumed 10 W of static power and 90 W of dynamic power. The Core i5 Ivy Bridge, released in 2012, had a clock rate of 3.4 GHz and voltage of 0.9 V. Assume that, on average, it consumed 30 W of static power and 40 W of dynamic power. For each processor find the average capacitive loads. Find the percentage of the total dissipated power comprised by static power and the ratio of static power to dynamic power for each technology.Amdahl’s Law is as applicable to software as it is to hardware. An oft-cited programming truism states that a program spends 90% of its time executing 10% of its code. Thus, tuning a small amount of program code can often have an enormous effect on the overall performance of a software product. Determine the overall system speedup if:Q.) 90% of a program is made to run 10 times as fast (900% faster).
- The same software is compiled on three computers A, B, and C with the clock frequency of 2GHZ, 2.5GHZ, and 3GHZ, respectively. On computer A, the software is compiled into 2 billion instructions with CPI of 1.1. On computer B, the software is compiled into 2.4 billion instructions with CPI of 1.2. On computer C, the software is compiled into 2.8 billion instructions with CPI of 1.2. We have (select all that apply) O the software runs fastest on computer A the software runs fastest on computer B the software runs fastest on computer C the software runs slowest on computer A the software runs slowest on computer B the software runs slowest on computer CSuppose that a bus has 16 data lines and requires 4 cycles of 250 nsecs each to transfer data. The bandwidth of this bus would be 2 Megabytes/sec. If the cycle time of the bus was reduced to 125 nsecs and the number of cycles required for transfer is doubled, what would the bandwidth of the bus? Select one: a.2 Megabytes/sec b.1 Megabytes/sec c.4 Megabytes/sec d.8 Megabytes/secA memory management system uses TLB (Translation lookaside buffer) to enhance memory access time. If time to access a TLB is x nanoseconds and time to access main memory is y nanoseconds (y >>x), determine effective memory access time when TLB hit ratio is p ( 0 < p <1)? Also, determine the effective memory access time when x = 1 nanosec, y=20 nanosec, and p = 0.7.