Consider the following duration for each stage: IF = 260 ns ID = 270 ns EX (addition) = 450 ns EX (subtraction) = 350 ns MEM = 200 ns WB = 290 ns Now answer the following question: By how many ns the single cycle datapath clock period is greater than the 5 stage pipeline clock period?

Systems Architecture
7th Edition
ISBN:9781305080195
Author:Stephen D. Burd
Publisher:Stephen D. Burd
Chapter4: Processor Technology And Architecture
Section: Chapter Questions
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Consider the following duration for each stage:

IF = 260 ns

ID = 270 ns

EX (addition) = 450 ns

EX (subtraction) = 350 ns

MEM = 200 ns

WB = 290 ns

Now answer the following question:

By how many ns the single cycle datapath clock period is greater than the 5 stage pipeline clock period?

***SHOW NECESSARY DIAGRAMS AND CALCULATIONS****

Subject: COMPUTER ARCHITECTUR

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