Assume a swapping system in which memory consists of the following hole sizes in memory and in order of 12K, 16K, 8K, 10K, 22K, 8K, 11K, 14K, and 13K. Which memory hole is taken for successive segment requests of (a) 7K (b) 30K (c) 20K (d) 6k (e) 2k for first fit, best fit, worst fit, and next fit.
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Q3: Assume a swapping system in which memory consists of the following hole sizes in memory and in order of 12K, 16K, 8K, 10K, 22K, 8K, 11K, 14K, and 13K.
Which memory hole is taken for successive segment requests of
(a) 7K
(b) 30K
(c) 20K
(d) 6k
(e) 2k
for first fit, best fit, worst fit, and next fit.
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- Q: Assume a swapping system in which memory consists of the following hole sizes in memory and in order of 12K, 16K, 8K, 10K, 22K, 8K, 11K, 14K, and 13K. Which memory hole is taken for successive segment requests of(a) 7K(b) 30K(c) 20K(d) 6k(e) 2kfor first fit, best fit, worst fit, and next fit.Consider a swapping system in which memory consists of the following hole sizes in memory order: 10 MB, 4 MB, 20 MB, 18 MB, 7 MB, 9 MB, 12 MB and 15 MB. Which hole is taken for successive segment requests of (i) 12 MB (ii) 10 MB (iii) 9 MB for first fit? Now repeat the question for best fit and worse fit.Consider a swapping system in which main memory contains the following hole sizes in memory order: 10K, 4K, 20K, 18K, 7K, 9K, 12K, and 15K. Which hole is taken for successive segment requests of (a) 12K, (b) 10K and (c) 9K for Worst-Fit ?
- Q3 Consider a swapping system in which main memory contains the following hole sizes in memory order: 10K, 4K, 20K, 18K, 7K, 9K, 12K, and 15K. Which hole is taken for successive segment requests of (a) 12K, (b) 10K and (c) 9K for Next-Fit? Assume the last allocated hole is 20K.A swapping system eliminates holes by compaction.Assuming a random distribution of many holes and many data segments and a time to read or write a 32 bit memory word of 14 uses about how long does it take to compact 4 GB. For simplicity assume that word O is part of a hole and that the highest word in memory contains valid dataConsider a DRAM chip of capacity 256 KB and each memory location contains 8 bits. The memory chip is organized in matrix form with equal number of rows and column for each memory location of 8 bits. This DRAM chip has a refresh interval of 64 ms, memory bus runs at 200 MHz, and the refresh cycle takes 4 clock cycle. a) Time required to refresh the DRAM chip. b) What is the minimum size of the refresh counter?
- Consider a swapping system in which memory consists of the following hole sizes in memory order: 10K, 4K, 20K, 18K, 7K, 9K, 12K, and 15K. Which hole is taken for successive segment requests of: (a) 12K (b) 10K (c) 9K, for first fit, best fit, worst fit? In the boxes, type answers without space i.e., if your answer is 10K, write as 10K and NOT 10 K (this will be marked incorrect) First Fit: (a): Best Fit: (a): Worst Fit: (a): (b): , (b): (b): (c): , (c): , (c):- Consider 7 memory partitions of size 470 KB, 400 KB, 600 KB, 200 KB, 500 KB, 300 KB and 250 KB. These partitions need to be allocated to 6 processes of sizes 190 KB, 491 KB, 468 KB and 210 KB, 357 KB and 587 KB in that order. Perform the allocation of processes using- First Fit Algorithm Best Fit Algorithm Worst Fit Algorithm 470 KB 400 KB 600 KB 200 KB 500 KB 300 KB 250 KB (190 KL) P1 491 KB P2 468 KB P3 (210 KB P4 357 KB) P5 587 KL P6A system is using segmentation to map physical memory. Current segment table is as follows. Some of the entries are stored in associative registers as given in second table. Assume that the register access time is 10 nanoseconds and memory access time is (10 x 7) nanoseconds; Find the physical memory address for each of the following logical memory addresses given by <Segment no, offset> Calculate effective memory access time for each (a) <0,3700> (b) <2,3780> (c) <1,200>
- a. We are given a system with 2 levels of cache, L1 and L2. The CPU directly interfaces to the L1 cache, which has a hit time of 1 ns and a hit rate of 0.4. On misses, the L1 accesses the L2 cache, which has an access time of 20 ns, and a hit rate of 0.8. If the L2 misses, it accesses the main memory, which has an access time of 100 ns. Determine the average memory access time, of the CPU to the memory hierarchy.b. A cache is inserted between the main memory, which is 32 MB, and the CPU. This cache can accomodate 64 blocks and each block can accomodate 128 words (2B per word). How many possible blocks can be stored in one cache block if it is a direct-mapped cache?Determine the effective CPI, MIPS rate, and execution time for this program. Consider two different machines, with two different instruction sets, both of which have a clock rate of 200 MHz. The following measurements are recorded on the two machines running a given set of benchmark programs: Instruction Count (millions) Instruction Type Machine A Arithmetic and logic Load and store Branch Others Machine A Arithmetic and logic Load and store Branch Others 8424 10 9824 Cycles per Instruction 1343 1243 4 a. Determine the effective CPI, MIPS rate, and execution time for each machine. b. Comment on the results.Consider the cache memory and the main memory connected serially. If the word in not found in cache memory, then it is found in the main memory. Let C1 and C2 be the cache memory in a two-level cache system. The access time of C1 is 3 cycle, access time of C2 is 15 cycle and the access time of main memory is 50 cycle. The miss rate of is 10% and 20% of C1 and C2 respectively. The average memory access time of the system is cycle.