Q5: By using Karanough map; Find: 1- The min. SOP for X. 2- The min. POS for X. 3- Draw the logic circuit diagram of step 1 using NAND gates only. 4- Draw the logic circuit diagram of step 2 using NOR gates only. X (A, B, C, D) = E(0, 2, 3, 4, 10, 11, 13, 15), with don't care Y (A, B, C, D) = E( 8, 12, 14)

Introductory Circuit Analysis (13th Edition)
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ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
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Q5: By using Karanough map; Find:
1- The min. SOP for X.
2- The min. POS for X.
3- Draw the logic circuit diagram of step 1 using NAND gates only.
4- Draw the logic circuit diagram of step 2 using NOR gates only.
X A, B , C, D) = Σ(0, 2 , 3, 4, 10, 11 , 13, 15),
with don't care Y (A, B, C, D) = E( 8, 12, 14)
Transcribed Image Text:Q5: By using Karanough map; Find: 1- The min. SOP for X. 2- The min. POS for X. 3- Draw the logic circuit diagram of step 1 using NAND gates only. 4- Draw the logic circuit diagram of step 2 using NOR gates only. X A, B , C, D) = Σ(0, 2 , 3, 4, 10, 11 , 13, 15), with don't care Y (A, B, C, D) = E( 8, 12, 14)
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