Lab1_report

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School

Iowa State University *

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Course

201

Subject

Electrical Engineering

Date

Apr 3, 2024

Type

pdf

Pages

6

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CprE 381, Computer Organization and Assembly Level Programming Lab 1 Report Student Name: Joseph Barnes III Submit a typeset pdf version of this on Canvas by the due date. Refer to the highlighted language in the lab document for the context of the following questions . [Part 1.c] Think of three more cases and record them in your lab report. Test case 3: s_iX <= 0; s_iW <= 2; s_iLdW <= 1; s_iY <= 0; wait for gCLK_HPER*2; Test case 4: s_iX <= 5; s_iW <= 0; s_iLdW <= 0; s_iY <= 11; wait for gCLK_HPER*2; wait for gCLK_HPER*2; Test case 5: s_iX <= 5; s_iW <= 2; s_iLdW <= 1; s_iY <= 3; wait for gCLK_HPER*2; wait for gCLK_HPER*2; end process; [Part 1.e] For labels 1, 7, 22, and 28, specify where (VHDL file and line number) these values are located – some will be found in more than one place. Also attempt to explain the functionality of each label as it occurs in the code Label 1 – In the attached file that was given label 1 is located on line 23 in the TPU_MV_Element.vhd Label 7 – In the attached file that was given label 7 is located on line 117 in the TPU_MV_Element.vhd Label 22 – In the attached file that was given label 22 is located on line 86 in the TPU_MV_Element.vhd Label 28 - In the attached file that was given label 28 is located on line 114 in the TPU_MV_Element.vhd
[Part 1.g.v] In your lab report, include a screenshot of the waveform. Describe, in plain English, any differences between what you expected and what the simulation showed. The expected output was 55, but the actual output was 33. The program verified that the timing is correct in the code, with 5 ns delay before the first cycle, 20 ns delay after the first cycle, and 40 ns delay after the second cycle. Despite this, the output doesn't match the expected result. [Part 1.h] In your lab report, include a screenshot of the waveform. Describe, in plain English, how your waveform matches the expected result (e.g., reference the specific cycles and times). In your submission zip file, provide the completed TPU_MV_Element.vhd file in a folder called ‘MAC’. This output is correct because after the three test cases run, the output is 55. [Part 3.a] Draw the truth table, Boolean equation, and Boolean circuit equivalent (using only two- input gates) that implements a 2:1 mux. Include this in your lab report. [Part 3.d] In your lab report, include a screenshot of the waveform. Make sure to label the screenshot with which module it is testing.
Above image is structural Mux2to1 waveform [Part 3.e] Again, in your lab report, include a labeled screenshot of the waveform showing the dataflow mux implementation working. Above image is dataflow Mux2to1 waveform [Part 4] Include a waveform screenshot and corresponding description demonstrating it is working correctly. The waveform displayed above corresponds to the Mux2to1_N operation. Its functionality is affirmed by the observed behavior: in the initial scenario, with the signal bit set to zero, it correctly selects D1 as the output; upon changing the signal bit to 1, the output appropriately switches to D0. [Part 5.b] Include a waveform screenshot and description in your lab report.
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