Computer Systems: A Programmer's Perspective (3rd Edition)
3rd Edition
ISBN: 9780134092669
Author: Bryant, Randal E. Bryant, David R. O'Hallaron, David R., Randal E.; O'Hallaron, Bryant/O'hallaron
Publisher: PEARSON
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Chapter 9.3, Problem 9.2PP
Program Plan Intro
Page table entries (PTEs):
A page table is a collection of page table entries. In the virtual address space, each page has a page table entries at a fixed offset.
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Students have asked these similar questions
Problem 0. The following table gives some of the parameters for a number of different hardware
caches. Fill in the table with the values of the missing parameters. Recall that m is the number of
physical address bits, C is the cache size in bytes, B is the block size in bytes, E is the associativity,
i.e., lines per set, S is the number of sets, t is the number of tag bits, s is the number of set index
bits, and b is the number of block offset bits.
Cache m
48
32030
(b)
48
32
24
24
C
B
E
16384 32 16
32768 64
65536 128
512 32
1024
8
8
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1
4
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b
S
t
Q.No.8: In paging (given
diagram), for CPU request
there are two access time one
for accessing page table and
one for physical memory
access.
physical
address f0000..0000
logical
address
CPU
a) How should we minimize
this access time? Redraw
1111...1111
the figure.
b) Formulate the formula for
Effective Access Time.
c) Calculate
Access Time (EAT) by
assuming the Hit ratio (a )
the Effective
physical
memory
85% and 95%. Cache
page table
Access Time (ɛ) is 20
microsecond and Memory
Access Time (T) is 100
microsecond.
I have a little bit problem with my late quiz for computer architecture, I get the answer from my lecturer but I still don't feel fully understand, can I ask for some help:
In a computer system, the memory has 32 blocks and the cache has 8 blocks. Assume there is only one word per block with 4 bytes in one word. The reference sequence in terms of word location is 0, 2, 4, 10, 5, 12, 8, 18, 13. If the cache is direct-mapped, how many misses do we have if the cache is initially empty? Can you give the hit or miss for each reference?
Chapter 9 Solutions
Computer Systems: A Programmer's Perspective (3rd Edition)
Ch. 9.2 - Prob. 9.1PPCh. 9.3 - Prob. 9.2PPCh. 9.6 - Prob. 9.3PPCh. 9.6 - Prob. 9.4PPCh. 9.8 - Practice Problem 9.5 (solution page 882) Write a C...Ch. 9.9 - Prob. 9.6PPCh. 9.9 - Prob. 9.7PPCh. 9.9 - Prob. 9.8PPCh. 9.9 - Prob. 9.9PPCh. 9.9 - Prob. 9.10PP
Ch. 9 - Prob. 9.11HWCh. 9 - Repeat Problem 9.11 for the following address....Ch. 9 - Repeat Problem 9.11 for the following address....Ch. 9 - Given an input file hello.txt that consists of the...Ch. 9 - Determine the block sizes and header values that...Ch. 9 - Prob. 9.16HWCh. 9 - Prob. 9.17HWCh. 9 - Prob. 9.18HWCh. 9 - Prob. 9.19HWCh. 9 - Write your own version of malloc and free, and...
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- Electrical Engineering 1.) Consider the following series of address references, given as byte addresses: 4. 16, 32, 20, 80, 68, 76, 224, 36, 44, 16, 172, 20, 24, 36, 68 Label each reference as a hit or miss, and show the final cache contents, for each of the following caches. Assume LRU replacement (where appropriate). a.) Direct-mapped, 16x 4-byte blocks. b.) Direct-mapped, 16-byte blocks, total size of 64 bytes. c.) Two-way set associative, 4-byte blocks, total size of 64 bytes. d.) Fully associative, 4-byte blocks, total size of 64 bytes.arrow_forward4. The following problems deal with translating from C code to MIPS code or MIPS code to C code. Assume that the signed variables f, g, h and i are assigned to registers $s0, $1, $2, $3 respectively. Assume the base address of the integer arrays A and B are in registers $s4 and $55 respectively. Translate the following MIPS code to C code. Please indicate which elements of integer array A and B are modified by this code. addi $t0, $1, 6 sll $t0, $t0, 4 add $t0, $t0, $5 Iw $t0, 0($t0) sw $t0, 4($4)arrow_forward6.40 Given the assumptions in Problem 6.38, determine the cache performance of the following code: for (1 = 0; i < 16; i++) { for (j = 0; j < 16; j++) { square [1] [j].y = 1; 1 2 3 4 0; i < 16; i++) { for (j - 0; j < 16; j++) { square [i] [j].c square [i] [j).m = 0; 0; 6 for (i 7 8 9 10 square[i] [j].k 11 12 A. What is the total number of writes? B. What is the total number of writes that miss in the cache? C. What is the miss rate?arrow_forward
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