You are asked to design a combinational circuit with three inputs x, y, z, and one output A. The output of the combinational logic circuit is equal to A = y +z (OR operation) when the binary value of x is 0 and the output is equal to A = (yz)' (NAND operation) when the binary value of x is 1. Construct the truth table for the given problem. x y z A 1 1 1 1 1 1 1 1 1 1
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- 8. Subtract the following 16-bit binary numbers. a. 11001011 00101000, - 10011110 01011011, b. 10111100 10111000; - 10011000 11110011,The input to a combinational logic circuit is 4-bit binary number (A, B, C, D). Design the circuit strictly using NAND gate with two outputs (Y1 and Y2) for the following conditions: Output Y1 is low when the input binary number is less than or equal to 7. Output Y2 is high when the input binary number is less than or equal to 7.) Assume A=A3A2A1A0, and B=B3B2B1B0 , both 4 bit binary numbers. If Y=3A+B, answer the following: Design a digital circuit that implements Y using the minimum hardware. You may use 4 bit adders, Half adders, Full adders, and a minimum number of logic gates as necessary. *(sketch your solution)
- Detecting and detecting 010011 sequence in binary information received from an external input line xFor sequential logic circuit that makes external z output 1 when it does; a) Create the state diagram. Explain how you created it. b) Create the situation table. Note: D flip-flops are used in this circuit. If not used in the status tableif there are cases, you can specify the next state values and output as neutral values.4. A combinational logic circuit that compares between two 2-bit numbers A (AI A0) and B (B1 B0) is designed. Output F is high when A > B and low when A < B. a. Are there any conditions which cause none of the outputs to be asserted? If the conditions exist, what are the inputs? b. Derive the truth table and obtain the maxterm notation for the output. c. Obtain the minimized POS expression of the logic circuit. d. Draw the logic circuit using basic gates.1. Gray code to Binary converter: Gray code is one of the codes used in digital systems. It has the advantage over binary numbers that only one bit in the code word changes when going from one number to the next. (See Table 1). Design a combinational circuit with 4 inputs and 4 outputs that converts a four- bit gray code number into an equivalent four-bit Binary number. Use Karnaugh map technique for simplification. Use LogicWorks for pre-lab demonstrations. Select the library "7400dev.clf* in the Parts Palette and then select the XOR chip 74-86. This would give you a set of 4 XOR's as shown in Fig. 1, just like the hardware chip 74-86. You could use as many as needed from these XOR gates in your design. Get back to ALL LIBRARIES and select switches for the inputs and Binary Probes as indicators of the outputs. Verify your design in the pre-Lab. During the Lab construct the circuit and verify its operations.
- T: Answer thne f. questions: 1) The hexadecimal number ´Al' has the decimal value equivalent to (A) 80 (B) 161 (C) 100 (D) 101 2) The output of a logic gate is 0 when all its inputs are logic 1. The logic is either (A) a NAND or an EX-OR (B) an OR or an EX-NOR (C) an AND or an EX-OR (D) an NOR or an EX-NOR 3) The Gray code of the Binary number 1100111 is (A) 1011011 (B) 1010100 (C) 1001001 (D) 101101 4) When simplified with Boollean Algebra (a+b)(a+c) simplifies to (A) a (B) a+a(b+c) (C) a(1+bc) (D) a+bc 5) -31 is represented as a sign Binary number ( using Sign-magnitude form ) equal to (A) 00011111 (B) 10101001 (C) 01110010 (D) 00101101 6) The Binary number 110111 is equivalent to decimal number (A) 25 (B) 55 (C) 26 (D) 34 7) With 4 bit, what the range of decimal values if the number is 2's complement signed number. (A) -32 to +31 (B) -2 to +1 (C) -8 to +7 (D) None of thesePlease design a 6:1 multiplexer following the below procedures with data inputs of D5, D4, D3,D2, D1, D0 and output of Y.1 How many select signals are needed for this Mux.2) List a truth table for this Mux. Note: for all the unused combinations of select signals, Y=D53) Develop an optimized function for this Mux.4) Sketch the logic diagram of implementing this 6:1 Mux.5) Write a complete VHDL structural model to implement the above 6:1 multiplexer. Assume allthe required sub-component (standard gates) VHDL models are given/known that you can useIn this problem we'll explore the fact that all logical circuits can be implemented using just NAND gates. The figure below shows you the symbol for a NAND gate and its truth table. We then show you how NAND gates can be wired together to perform the equivalent of a NOT gate, an AND gate, and an OR gate. NAND gate AB Output 1 01 1 Inputa Inputg Output 10 1 11 NOT A- AND D B. A. OR B. 2 i. Let's denote p NAND q as pīq. Write a logical expression for the thrce circuits corresponding to AND, OR, and NOT. ii. Validate your three logical expressions with three truth tables. For clarity and full credit, show cach variable and distinct sub-clause in a separate column, culminating in your final formula. 3. 2.
- Grey converters are often used in industrial circuits where the normal sequence of binary numbers may produce ambiguity during transition. This is elliminated with the Grey code, as only one bit changes, during a normal transition of sequential numbers. Show the logic required to convert a 10-bit binary number to Gray code and use that logic to convert the following to Gray code: a) 1010101010 b) 1111100000 c) 0000001110 d) 11111111113. Logic Design a. Create the truth table of a 3-input AND gate. Realize the 3-input AND operation using only 2-input NOR gates. b. Create the truth table of a 3-input OR gate. Realize the 3-input OR operation using only 2- input NAND gates. c. Using AND and OR logic gates, implement the logic function: F(x, y, z) = xy + yz + zx d. Using NAND logic gates, implement the logic function: F(x, y, z) = xy + yz + zxCreate a truth table with four inputs A, B, C and D and one output, Y. The output is FALSE only when A B and C=D. Otherwise the output is TRUE. Draw the Kamaugh map. write the simplified SOP expression and sketch the gate-level schematic.