Write VHDL code for an n-bits register (n can be 4, 8, 16, …) with the Synchronous Reset Active High, and Load Input Active High.
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Write VHDL code for an n-bits register (n can be 4, 8, 16, …) with the Synchronous Reset Active High, and Load Input Active High.
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- Write VHDL code for a modulo-13 counter (counting sequence is 010, 110, …. 1210). The counter has the following features: a synchronous Active High Reset a value R can be loaded into the counter, using the signal Ld (Load) The signal Ld is active High Draw the schematic of your counter, showing the inputs and outputs. Show the number of bits for R, Q (output of the counter), Ld.2-bit by 2-bit binary multiplier using ROM VHDL codeExample Assuming that a 3-bit ADC channel accepts analog input ranging from 0 to 5volts, determine a- The number of quatization levels b- The step size of the quantizer or resolution. c- The quantization level when the analog voltage is 3.2 volts. d- The binary code produced by the ADC. e- The quatization error when the analog voltage is 3.2 volts.
- Write VHDL code for an n-bits register (n can be 4, 8, 16, …) with the Synchronous Reset Active Low, and Load Input Active Low.4. Write AVR Assembly instructions make Port-D Pin-5 Output and set it High:Which statement is not true for a source encoder? a.reduces the size of the data b.Converts analog information to discrete signal c.Removes redundancy d.Converts digital input to pulsating signal
- 4) Write the function table for the given 1-bit ALU in the figure. Ainvert Binvert LO B invert Carry in (MUX) Carryin CarryOut Operation Operation (MUX) Result AND OR ADD SUB NAND NOR ResultQ2) A) Based on the count sequence and decoding operations of 74LS90S ICs shown in Figure below. Q2) B) Use the SAR ADC to convert the analog voltage of (7.28 V) to 8-bit binary. If (VREF = 10V), determine the final %3D binary answer and the percent error. 01011101, 0.1974588% 11011101, 0.1974588% 01011111, 0.1974588% 01111101, 0.1974588%1- What does the VOH parameter of a logic IC refer to? a) The highest permissible output voltage. b) The lowest output voltage recognized as logic 1. c) The highest output voltage recognized as logic 1. d) The highest output voltage recognized as logic 0. 2- Which of the following refers to the noise margin of a logic gate? a) The difference between VIH and VOL b) The difference between VOH and VOL c) The difference between VOH and VIH d) The difference between VIH and VIL 3- How many 74LS00 NAND gate inputs can be driven by a 74LS00 NAND gate outputs Refer to data sheet of 74LS00, the maximum values of IOH = 0.4 mA, IOL = 8 mA, IH = 20 μA, and IL = 0.4 mA. 4- The data sheet of a quad two-input NAND gate specifies the following parameters: IOH (max.) 0.4 mA, VOH (min.) 2.7 V, VIH (min.) =2V, VIL (max.) 0.8 V, VOL (max.) 0.4 V, IOL (max.) 8 mA, IL (max.)=0.4 mA, IIH (max.)-20µA, ICCH (max.) 1.6 mA, ICCL (max.) 4.4 mA, tpLH =pHL=15 ns and a supply voltage range of 5…
- Construct 3 input NAND using Register Transistor Logic (RTL).Write a Verilog code with testbench for 16-bit up/down counter with synchronous reset and synchronous up/down.If up/down is set the counter is up counter and if it is not set, the counter is a down counter. submit the module code, testbench code, and the simulation results. PLEASE EXECUTE CODE IN VERILOGQ2/ The information in an analog signal voltage waveform is to be transmitted over a PCM system with an accuracy of ±0.1% (full scale). The analog voltage waveform has a bandwidth of 100 Hz and an amplitude range of -10 to +10 volts. Find the minimum sampling rate required. i) ii) Find minimum bit rate required in the PCM signal. Find the number of bits in each PCM word. iii) iv) Find the minimum absolute channel bandwidth required for the transmission of the PCM signal.