We can improve the floating point instruction performance of machine by a factor of 6 (the same floating point instructions run 6 times faster on this new machine). What percent of the instructions must be floating point to achieve a Speedup of at least 2?
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We can improve the floating point instruction performance of machine by a
factor of 6 (the same floating point instructions run 6 times faster on this new machine). What percent of
the instructions must be floating point to achieve a Speedup of at least 2?
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Solved in 2 steps
- You must show all work for every problem that requires it. The point values for problems may be changed at the professor's discretion. Read each question carefully and follow the instructions. A computer hardware as the following latency for its instructions in Pico seconds: Type Instruction Memory Register Read ALU Operation Data Memory Register Write Total R-Format 250 150 200 0 20 620 lw 250 150 200 250 20 870 sw 250 150 200 250 0 850 beq 250 150 200 0 0 600 J 250 0 0 0 0 250 For a single-cycle implementation what Clock Rate does the machine needs to operate at? For a multi-cycle implementation what Clock Rate does the machine needs to operate at? Provide the type, assembly language instruction and binary representation of instructions described by the following MIPS fields: Op=0x0, rs=3, rt=2, rd=3, shamt=0, funct=34 Op=0x23, rs=3, rt=1, const=0x4 In the snippet of assembly code below, how many times is…Suppose that we are developing a new version of the AMD Barcelona proces- sor with a 4 GHz clock rate. We have added some additional instructions to the instruction set in such a way that the number of instructions has been reduced by 15% from the values shown for each benchmark in Exercise 1.12. The execution times obtained are shown in the following table. a. Name Execution Time (seconds) Reference Time (seconds) bzip2 700 9650 SPECratio 13.7 1.13.2 [10] In general, these CPI values are larger than those obtained in previous exercises for the same benchmarks. This is due mainly to the clock rate used in both cases, 3 GHz and 4 GHz. Determine whether the increase in the CPI is similar to that of the clock rate. If they are dissimilar, why?Given clock = 10MHZ, what is instruction cycle? Please show how to generate 1 second delay. (You can show your idea only or show the codes.)
- When making changes to optimize part of a processor, it is often the case that speeding up one type of instruction comes at the cost of slowing down something else. For example, if we put in a complicated fast floating point unit, that takes space, and something might have to be moved farther away from the middle to accommodate it, adding an extra cycle in delay to reach that unit. The basic Amdahl?s law equation does not take into account this trade-off. a. If the new fast floating point unit speeds up floating point operations by, on average 2x, and floating operations take 20% of the original program's execution time, what is the overall speedup (ignoring the penalty to any other instructions)? b. Now assume that speeding up the floating point unit slowed down data cache accesses, resulting in a 1.5x (0r 2/3 speedup). Data cache accesses consume 10% of the execution time. What is the overall speedup now? c. After implementing the new floating point operations, what percentage of…In this case, every instruction receives its own data, independent of how the data for other instructions is obtained. We make advantage of a: A Multiple Data/Instruction B Multiple Iterations of Data or Instruction C Singular Data Single Inst D Singe Inst Multiplewhat is the instruction format of the operation below and how the CPU fetch this operands from memory? Explain that. A = X-Y/Z *
- Do you know what would happen if an instruction was rejected? TLBs controlled by software are quicker than those controlled by hardware in the following situations:4. A benchmark program is run on an 80 MHz processor. Based on the recorded measurements shown below, determine the effective CPI, MIPS rate, and execution time for this program. Instruction Type Instruction Count CPI Integer Arithmetic 30,000 1 Data Transfer 45,000 2 Floating Point 15,000 2 Control Transfer 10,000 2 Show your work for credit. Effective CPI: MIPS rate: Execution timeTwo word-wide unsigned integers are stored at the memory addresses 0A00 H and 0A02 H respectively, Write an instruction sequence that computes and stores their sum, difference, product, and quotient then Store these results at consecutive memory locations starting at address 0A10 H in memory. To obtain the difference, subtract the integer at 0A02 H from the integer at 0A00 H. For the division, divide the integer at 0A00H by the integer at 0A02 H. Use register indirect relative addressing mode to store the various result.
- For the instruction add $t0, $s0, $s1, what is the range(s) of values for $s1 that would result in overflow?For a computer's instruction set to be orthogonal, it must be able to generate a "backup" instruction for each main instruction. Please correct me if I am in error.To define an Instruction Length, we look at the following: Identify two constraints imposed by the design that increase the need for, or the size of, the manual and explain how you overcame them.