ve a two-level page table where the first level is indexed by 15-bits, then how many entries does the first-level page table
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Suppose that a machine has 42-bit virtual addresses and 32-bit physical addresses.
{a} How much RAM can the machine support (each byte of RAM must be addressable)?
{b} What is the largest virtual address space that can be supported for a process?
{c} If pages are 2 KB, how many entries must be in a single-level page table?
{d} If pages are 2 KB and we have a two-level page table where the first level is indexed by 15-bits, then how many entries does the first-level page table have?
{e} With the same setup as part {d}, how many entries are in each second-level page table?
{f} What is the advantage of using a two-level page table over single-level page table?
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- If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the fetch cycle is 40% of the processor cycle time, what memory access speed is required to implement load operations with zero wait states and load operations with two wait states?Consider a computer system with a 30-bit logical address and 4-KB page size. The system supports up to 512 MB of physical memory. How many entries are there in each of the following? Assume that each page table entry is 4 Bytes. c. A conventional single-level page table?d. An inverted page table?e. A two-level hierarchical page table? Consider a virtual memory system with a 50-bit logical address and a 38-bit physical address. Suppose that the page/frame size is 16K bytes. Assume that each page table entry is 4 Bytes. a. How many frames are in the systems? How many pages in the virtual address space for a process? b. If a single-level page table is deployed, calculate the size of the page table for each process. c. Design a multilevel page table structure for this system to ensure that each page table can fit into one frame. How many levels do you need? Draw a figure to show your page systemsConsider an operating system that uses 48-bit virtual addresses and 16KB pages. The system uses a multi-level page table design to store all the page table entries of a process, and each page table entry and index entry are 4 bytes in size. What is the total number of page that are required to store the page table entries of a process, across all levels of the page table? You may follow the hint below or finish from scratch to fill the blanks. Please show your calculations to get partial points like 2^10/2^4=2^6. 1. We need to calculate the total number of page table entries needed for a process (i.e., the total number of pages for a process) 2. We need to calculate how many entries each page can store 3. With 1 and 2, we can calculate how many pages needed for the lowest (innermost) level 4. Each page from 3 requires an entry (pointer) in the upper (next) level. We need to calculate how many pages are required to store this next level entries (please note the entry size is always 4…
- Suppose a computer using fully associative cache has 224 words of main memory and a cache of 512 blocks, where each cache block contains 16 words. How many blocks of main memory are there? What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag and offset fields? To which cache block will the memory reference 17042416 map?Suppose a computer using direct mapped cache has 232232 words of main memory and a cache of 1024 blocks, where each cache block contains 32 words. How many blocks of main memory are there? What is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, block, and word fields? To which cache block will the memory reference 000063FA16 map?Suppose a computer using set associative cache has 216 words of main memory and a cache of 128 blocks, and each cache block contains 8 words. If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields?
- Question 8: A CPU generates 32-bit virtual addresses. The page size is 4 KB. The processor has a translation look-aside buffer (TLB) which can hold a total of 128 page table entries and is 4-way set associative. The minimum size of the TLB tag is: 01 02 0 3 04 1. 11 bits 2. 13 bits 3. 15 bits 4. 20 bits9. Consider a system that uses 32-bit addresses and page table structures as discussed in class. If the address space of a process contains exactly 256 pages, what is the minimum number of pages that might be needed for its page table structure? What is the maximum number that might be needed? Briefly explain your answer.Suppose a computer using direct mapped cache has 232 words of main memory, and a cache of 1024 blocks, where each cache block contains 32 words. How many blocks of main memory are there? What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag, block, and offset fields? To which cache block will the memory reference 0003101A16 map?
- Suppose a computer system uses 16-bit addresses for both its virtual and physical addresses. In addition, assume each page (and frame) has size 256 bytes. How many bits are used for the page number? How many bits are used for the offset? With this system, what’s the maximum number of pages that a process can have? Suppose that each entry in the page table comprises 4 bytes (including the frame number, the valid bit, and miscellaneous “bookkeeping bits”). An OS uses an array to store the page table. What is the size of the page table? Furthermore, suppose the first 6 pages of a process map to frames 222 to 227 (as decimal numbers), and the last 5 pages of the process map to frames 1 to 5 (also decimal numbers). All other pages are invalid. Draw the page table, including the valid bit and the frame number.Suppose a computer using fully associative cache has 4G bytes of byte-addressable main memory and a cache of 512 blocks, where each cache block contains 128 bytes. a) How many blocks of main memory are there? b) What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag and offset fields? c) To which cache block will the memory address 0x018072 map?Consider a machine with a byte addressable main memory of 216 bytes and block size of 8 bytes. Assume that a direct mapped cache consisting of 32 lines is used with this machine. a. How is a 16-bit memory address divided into tag, line number, and byte number? b. Into what line would bytes with each of the following addresses be stored? 0001 0001 0001 1011 1100 0011 0011 0100 1101 0000 0001 1101 1010 1010 1010 1010 c. Suppose the byte with address 0001 1010 0001 1010 is stored in the cache. What are the addresses of the other bytes stored along with it? d. How many total bytes of memory can be stored in the cache? e. Why is the tag also stored in the cache?