Two threads (A and B) are concurrently running on a dual-core processor that implements a sequentially consis-tent memory model. Assume that the value at address (R10) is initialized to 0. The instruction st immediate,(R10) writes an immediate number into the memory address stored in R10.Thread A (core 1)1: st 0x1, (R10)2: ld R1, (R10)3: st 0x2,ld R2,(R10)4:(R10)Thread B (core 2)1: st 0x3, (R10)2: ld R3, (R10)3: st 0x4,(R10)4: ld R4, (R10)After both threads have finished executing, you find that (R1, R2, R3, R4) = (1, 2, 3, 4). How many differentinstruction interleavings of the two threads produce this result (please show all possible interleavings)?

SOLUTION -There are two threads given-Thread AX1 : s t 0x1 , ( 0 x1000 )X2 : l d $r1 , ( 0 x1000…

Two threads (A and B) are concurrently running on a dual-core processor that implements a sequentially consis- tent memory model. Assume that the value at address (R10) is initialized to 0. The instruction st immediate, (R10) writes an immediate number into the memory address stored in R10. Thread A (core 1) 1: st 0x1, (R10) 2: ld R1, 3: st 0x2, 4: ld R2, (R10) (R10) (R10) Thread B (core 2) 1: st 0x3, (R10) 2: ld R3, (R10) 3: st 0x4, (R10) 4: ld R4, (R10) After both threads have finished executing, you find that (R1, R2, R3, R4) = (1, 2, 3, 4). How many different instruction interleavings of the two threads produce this result (please show all possible interleavings)?

Two threads (A and B) are concurrently running on a dual-core processor that implements a sequentially consis- tent memory model. Assume that the value at address (R10) is initialized to 0. The instruction st immediate, (R10) writes an immediate number into the memory address stored in R10. Thread A (core 1) 1: st 0x1, (R10) 2: ld R1, 3: st 0x2, 4: ld R2, (R10) (R10) (R10) Thread B (core 2) 1: st 0x3, (R10) 2: ld R3, (R10) 3: st 0x4, (R10) 4: ld R4, (R10) After both threads have finished executing, you find that (R1, R2, R3, R4) = (1, 2, 3, 4). How many different instruction interleavings of the two threads produce this result (please show all possible interleavings)?

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter11: Operating Systems

Section: Chapter Questions

Problem 21VE

See similar textbooks

Similar questions

A virtual memory has a page size of 16 words. There are 8 pages and 4 blocks. The associative memory page table contains the following entries. (Addresses are given HEX form): Page Block a) For the following virtual addresses find the CPU addresses: 3A, 5B, 1 3 b) For the following CPU addresses find the virtual addresses: 0C, 2D 1 4
In the S/370 architecture, a storage key is a control field associated with each page- sized frame of real memory. Two bits of that key that are relevant for page replace- ment are the reference bit and the change bit. The reference bit is set to 1 when any address within the frame is accessed for read or write, and is set to 0 when a new page is loaded into the frame. The change bit is set to 1 when a write operation is per- formed on any location within the frame. Suggest an approach for determining which page frames are least-recently-used, making use of only the reference bit.
In a main memory-disk virtual storage system, the page size is 1KByte and the FIFO algorithm is used for page replacements. A given program has been allocated three page frames in the main memory and it makes the following 16 memory references when it starts executing (the addresses are given in decimal):500, 2000, 2500, 800, 4000, 1000, 5500, 1500, 2800, 400, 5000, 700, 2100, 3500, 900, 2400 Fill in the contents of the three page frames after each memory reference in a table and calculate the hit ratio. Hint: denote by 'a' the page consisting of locations 0 through 1023 in memory. Similarly, b: 1024-2047, c: 2048-3071, d: 3072-4095, e: 4096-5119 and f: 5120-6143. Round to three decimal places.
A computer system has the segmented paging for virtual memory. The memory is byte addressable. Both virtual and physical address spaces contain 216 bytes each. The virtual address space is divided into 8 non-overlapping equal size segments. The memory management unit has a hardware segment table, each entry of which contains the physical address of the page table for the segment. Page tables are stored in the main memory and consists of 2 byte page table entries What is the minimum page size in bytes so that the page table for a segment requires at most one page to store it and also give the division of virtual address ?
Assume that an interrupt mechanism uses the hardware stack to store PC and other registers of the interrupted computations. The interrupt mechanism recognizes 4 interrupt vectors IV [1], IV [2], IV [3], IV [4] initialized by addresses of their corresponding ISRI=1.4. The elements of the hardware stack are a record R, where each field stores a specific CPU register (R.PC is the field, which stores the program counter PC and so on). The Hardware stack is manipulated using the standard stack operation Pop, Push, EmptyStack. a) Explain how the CPU detects an interrupt signal I and what actions should be taken ? b) Write the initial and final sequences of instruction of a given ISR I. (Transparency). c) Write the ISR4 such that whatever number of interrupted computation (in the stack) it gives the control to the first one interrupted.
Suppose a computer using fully associative cache has 220 words of main memory and a cache of 128 blocks, where each cache block contains 16 words. (a) How many blocks of main memory are there? (b) What is the format of a memory address as seen by the cache, that is, what are the sizes of the tag and word fields? (c) To which cache block will the memory reference 01D872_{16} map?
Suppose a computer using fully associative cache has 224 words of main memory and a cache of 512 blocks, where each cache block contains 16 words. How many blocks of main memory are there? What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag and offset fields? To which cache block will the memory reference 17042416 map?
In computer architecture, SIMD may refer to the situation where. a) multiple CPU cores can access the same memory concurrently. b) the same operation can be applied to multiple operands with only a single instruction. c) multiple independent instructions can be executed at the same time in the same CPU core. d) multiple independent memory banks show up as a single address space.
Assume that an interrupt mechanism uses the hardware stack to store PC and other registers of the interrupted computations. The interrupt mechanism recognizes 4 interrupt vectors IV [1], IV [2], IV [3], IV [4] initialized by addresses of their corresponding ISR I =1..4. The elements of the hardware stack are a record R, where each field stores a specific CPU register (R.PC is the field, which stores the program counter PC and so on). The Hardware stack is manipulated using the standard stack operation Pop, Push, EmptyStack.a) Explain how the CPU detects an interrupt signal I and what actions should be taken?b) Write the initial and final sequences of instruction of a given ISR I (Transparency).c) Write the ISR4 such that whatever number of interrupted computation (in the stack) it gives the control to the first one interrupted.
Suppose a computer using set associative cache has 216 words of main memory and a cache of 128 blocks, and each cache block contains 8 words. If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields?
5. The stack memory is addressed by a combination of the segment plus_ offset. 6. The PUSH and POP instructions always transfer -bit number between the stack and a register or memory location in the 8086 microprocessors. 7. For string instructions, DI always addresses data in the segment. 8. The 8086 LOOP instruction decrements register and tests it for a 0 to decide if a jump occurs 9. The last executable instruction in a procedure must be 10.A bus cycle is equal to clocking. periods. 11. If A0 is a logic 0, then the memory bank is selected. 12.the 8086 processor is partitioned into two logical units------------ and C. 13. ------- is the value of the control word register (CWR) of PPI 8255 if all ports are input 14.Fixed address for I/O instructions bytes while Variable address for --- --- ---bytes I/O instructions is 15. Write bus cycle need -clocks to complete one write of data to memory
In a main memory-disk virtual storage system, the page size is 1KByte and the OPTIMAL algorithm is used for page replacements. A given program has been allocated three page frames in the main memory and it makes the following 16 memory references when it starts executing (the addresses are given in decimal):500, 2000, 2500, 800, 4000, 1000, 5500, 1500, 2800, 400, 5000, 700, 2100, 3500, 900, 2400 Fill in the contents of the three page frames after each memory reference in a table and calculate the hit ratio. Hint: denote by 'a' the page consisting of locations 0 through 1023 in memory. Similarly, b: 1024-2047, c: 2048-3071, d: 3072-4095, e: 4096-5119 and f: 5120-6143. Round to three decimal places.