11.3 This problem illustrates the improper operation that can occur if both inputs to an S-R latch are 1 and are then changed back to 0. For Figure 11-6, complete the follow- ing timing chart, assuming that each gate has a propagation delay of exactly 10 ns. Assume that initially P = 1 and Q = 0. Note that when t = 100 ns, S and R are both changed to 0. Then, 10 ns later, both P and Q will change to 1. Because these 1's are fed back to the gate inputs, what will happen after another 10 ns? S R P 0 50 100 150 140 200 t(ns)

The following circuit shows the carry-lookahead adder design. Assuming the delay for each gate is 2.2 ns, and there is no fan-in issue (meaning a gate can take as many inputs as possible). Consider a n-bit carry-lookahead adder, what is the duration (in ns) you have to wait until the correct C is generated? Carry-Lookahead Adder Ci+1=g; +pi ci = 8; + Pi (8-1 + Pi-1 C1.1) g+Pi8-1 + PiPi-11-1 = 81+Pi81-1+ Pi Pi-181-2+...+P1 Poco g₁ = xi yi Pi = x; + yi 2.2*(3+7*2) 2.2*3 2.2*8*n 2.2 n "

The circuit of Exp #8.2, configured as a subtractor, can be used to compare two 4-bit numbers. Subtractor outputs Cout and (S3.so) can be combined logically to indicate the relationship between inputs A and B. The gate circuit needed to do this appears as the interface block in the following diagram. Subtractor 220 ohm Cout A - B LEDO 4 A S3 A < B LED1 220 ohm Interface Block S2 (Your Design) 220 ohm B S1 A > B LED2 So (A - B) AirSupplyLab.com Figure 8.2: 4-bit Comparator Design the contents of this interface. You will build the circuit using only 2 chips: 1. a 7402 NOR chip 2. either a 7432 OR chip or a 7408 AND chip. Design the interface two ways: (a) an OR and NOR circuit, and (b), a NOR and AND circuit. Include both designs in your lab notebook and build and test one of them. Each design consists of 3 parts – one for each output – and requires 5 gates total. ExpressSCH has custom DM symbols for all gates (including ANDS and ORs). Use them, but only where they make circuit…

Question 5: F(a,b,c,d)=I(0,1,3,6,10,11,14) Implement the above boolean function using a. 4:1 MUX(s) and 2:1 MUX(s) [both in the same circuit]. b. 8:1 MUX You can also use minimal number of BASIC gate(s) with the above-mentioned decoders.