The following diagram shows some registers like processor registers R1 and R2, Program counter PC and Index Register XR along with their corresponding values. It also shows a memory with some instructions like instruction A and next instruction.The memory holds instruction B which consists of four fields as given above. First field of instruction represents the addressing Mode (I), second field specifies Opcode (operation code) ADD representing operation addition, the third field represents Address field 1 and the fourth field represents Address field 2. Consider the following addressing modes, evaluate the result of execution of above instruction by giving steps of evaluation for each addressing mode for the scenario given above. Immediate Mode  Direct Mode Register Relative Mode Index ModeNote: Choose your own values for variables k – w, T1, T2. Choose any one of the given value for T3 (200 or 300). PC101Instruction B102Next InstructionR1 = T1200K250R2 = T2300M302NXR = T3400402P500600R602650700800VInstruction BModeADD200300(1)(Opcode)(Address field 1)(Address field 2)The memory holds instruction B which consists of four fields as given above. Firstfield of instruction represents the addressing Mode (1), second field specifiesOpcode (operation code) ADD representing operation addition, the third fieldrepresents Address field 1 and the fourth field represents Address field 2. Considerthe following addressing modes, evaluate the result of execution of aboveinstruction by giving steps of evaluation for each addressing mode for the scenariogiven above.Immediate ModeDirect ModeRegisterRelative ModeIndex ModeNote: Choose your own values for variables k- w, T1, T2. Choose any one of the given value forT3 (200 or 300).(50 marks) 3. The following diagram shows some registers like processor registers R1 and R2, Program counterPC and Index Register XR along with their corresponding values. It also shows a memory withsome instructions like instruction A and next instruction.

Part(a) The addressing modes refer to the many methods in which operands are declared in an…

The following diagram shows some registers like processor registers R1 and R2, Program counter PC and Index Register XR along with their corresponding values. It also shows a memory with some instructions like instruction A and next instruction. The memory holds instruction B which consists of four fields as given above. First field of instruction represents the addressing Mode (I), second field specifies Opcode (operation code) ADD representing operation addition, the third field represents Address field 1 and the fourth field represents Address field 2. Consider the following addressing modes, evaluate the result of execution of above instruction by giving steps of evaluation for each addressing mode for the scenario given above.  Immediate Mode  Direct Mode  Register  Relative Mode  Index Mode Note: Choose your own values for variables k – w, T1, T2. Choose any one of the given value for T3 (200 or 300).

The following diagram shows some registers like processor registers R1 and R2, Program counter PC and Index Register XR along with their corresponding values. It also shows a memory with some instructions like instruction A and next instruction. The memory holds instruction B which consists of four fields as given above. First field of instruction represents the addressing Mode (I), second field specifies Opcode (operation code) ADD representing operation addition, the third field represents Address field 1 and the fourth field represents Address field 2. Consider the following addressing modes, evaluate the result of execution of above instruction by giving steps of evaluation for each addressing mode for the scenario given above.  Immediate Mode  Direct Mode  Register  Relative Mode  Index Mode Note: Choose your own values for variables k – w, T1, T2. Choose any one of the given value for T3 (200 or 300).

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

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The following diagram shows some registers like processor registers R1 and R2, Program counter PC and Index Register XR along with their corresponding values. It also shows a memory with some instructions like instruction A and next instruction. The memory holds instruction B which consists of four fields as given above. First field of instruction represents the addressing Mode (I), second field specifies Opcode (operation code) ADD representing operation addition, the third field represents Address field 1 and the fourth field represents Address field 2. Consider the following addressing modes, evaluate the result of execution of above instruction by giving steps of evaluation for each addressing mode for the scenario given above. Ø Immediate Mode Ø Direct Mode Ø Register Ø Relative Mode Ø Index Mode Choose your own values for variables (v – w), T1, T2. Choose any one of the given value for T3 (200 or 300). V=600 W=770 T1=200 T2=200 T3=300
QuedT: Choose the correct answer: [ Opcode, funct3 and funct7/6 in instruction format are used to identify the: (a) function. (b) instruction. (e) branch. (d) memory address. The register that hold the address of the current instruction being executed is called: (a) saved register. (b) global pointer. (e) stack pointer. (d) program counter. Placing the executable file into the memory for execution by the processor is the role of (a) assembler. (b) linker. (e) loader. (d) compiler. The part which responsible for transmitting the data to/from the processor is: (a) control unit. (b) Datapath. (c) data bus. (d) memory. Parallel hardware cannot be used for faster division because: (a) subtraction is conditional on sign of remainder. (b) multiplication is conditional on sign of remainder. (c) subtraction is conditional on sign of divisor. (d) multiplication is conditional on sign of divisor. we cannot slower the clock cycle to fit the floating-point adder algorithm into one clock cycle…
In this classification, each instruction is executed uşing its own input data, independently of how other instructions get their data. We are using a(n): A Multiple Instruction Multiple Data. B Multiple Instruction Multiple Data. C Single Instruction Single Data. D Single Instruction Multiple Data
Iwill all steps for The following diagram shows some registers like processor registers R1 and R2, Program counter PC and Index Register XR along with their corresponding values. It also shows a memory with some instructions like instruction A and next instruction. The memory holds instruction B which consists of four fields as given above. First field of instruction represents the addressing Mode (I), second field specifies Opcode (operation code) ADD representing operation addition, the third field represents Address field 1 and the fourth field represents Address field 2. Consider the following addressing modes, evaluate the result of execution of above instruction by giving steps of evaluation for each addressing mode for the scenario given above. Ø Immediate Mode Ø Direct Mode Ø Register Ø Relative Mode Ø Index Mode Choose your own values for variables (v – w), T1, T2. Choose any one of the given value for T3 (200 or 300). V=700 W=870 T1=100 T2=200 T3=300
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Choose the correct answer: Opcode, funct3 and funct7/6 in instruction format are used to identify the: ● (a) function. (b) instruction. (c) branch. (d) memory address. The register that hold the address of the current instruction being executed is called: (a) saved register. (b) global pointer. (e) stack pointer. (d) program counter. Placing the executable file into the memory for execution by the processor is the role of: (a) assembler. (b) linker. (e) loader. (d) compiler. ● The part which responsible for transmitting the data to/from the processor is: (a) control unit. (b) Datapath. (c) data bus. (d) memory. ● ● Parallel hardware cannot be used for faster division because: (a) subtraction is conditional on sign of remainder. (b) multiplication is conditional on sign of remainder. (c) subtraction is conditional on sign of divisor. (d) multiplication is conditional on sign of divisor. ● we cannot slower the clock cycle t fit the floating-point adder algorithm into one clock cycle…
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