the follo modu input

Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
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Need help - verilog

Consider the following Verilog code:
always@ (*)
begin
if (c) x = m[3:2] | m[1:0];
else x = m[2:1] ^ 2'd3;
module ALU (a, b, c, x)
input [3:0] a, b;
input c;
output reg [1:0] x;
wire [3:0] m;
end
assign m = a & b;
endmodule
What will the value of x be if a=4'b1100, b=4'b1010 and c = 1? Give answer in binary form (ex: 11).
Transcribed Image Text:Consider the following Verilog code: always@ (*) begin if (c) x = m[3:2] | m[1:0]; else x = m[2:1] ^ 2'd3; module ALU (a, b, c, x) input [3:0] a, b; input c; output reg [1:0] x; wire [3:0] m; end assign m = a & b; endmodule What will the value of x be if a=4'b1100, b=4'b1010 and c = 1? Give answer in binary form (ex: 11).
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