Suppose we have a byte-addressable computer with a cache that holds 16 blocks of 4 bytes each. Assuming address has 8 bits, to which cache set would the hexadecimal address OxBE map if the computer mapping? that each memory uses 2-way set associative
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- Given a computer with a memory system having a40_bit address, a cache consisting of 8192 blocks each is 32 words. For the following cache types: Direct Mapped (DM), Fully_ associative (FA), Two_way set associative (2_way), Four_way set associative (4_way), Eight_way set associative (8_way), calculate the following values as specified. (Use paper and pencil to do needed calculations and write only the final answer in the given blank space). 1) DM: The size of the index field = Blank 1bits 2) 2_way: The size of the index field =Blank 2bits 3) 4_way: The size of the index field =Blank 3bits 4) 8_way: The size of the index field =Blank 4bits 5) The size of the offset field = Blank 5bits 6) DM: The size of the tag field =Blank 6bits 7) 2_way: The size of the tag field =Blank 7bits 8) 4_way: The size of the tag field =Blank 8bits 9) 8_way: The size of the tag field =Blank 9bits 10) FA: The size of the tag field =Blank 10bitsA cache memory has a line size of eight 64-bit words and a capacity of 4K words. The main memory size that is cacheable is 1024 Mbits. Assuming 4-way set associative mapping and that the addressing is done at the byte level. What is the format of the main memory addresses (i.e s-d, d, and w)? For the hexadecimal main memory location 2BFACEDH, find the corresponding 4-way set-associative memory formatConsider a fully-associative cache of size 4. Each slot in the cache can have just one item (i.e. the line size is 1 item). The cache is empty to start with. The cache uses an LRU replacement policy: every slot has a counter; every time a slot is accessed, a global counter is incremented and the value is stored in the slot counter; the slot with the lowest counter value is chosen for replacement. Sequence Id 1 2 3 4 5 6 7 8 10 Address Ox0012 0x0014 Ox0016 Ox0018 0x0016 0x0012 0x0020 Ox0022 0x0014 Ox0012 Hit/Miss Accesses 1 to 10 are respectively: Select one: O a. Miss, Miss, Miss, Miss, Hit, Hit, Miss, Miss, Miss, Miss O b. Miss, Miss, Miss, Miss, Hit, Hit, Miss, Miss, Hit, Hit O. Miss, Miss, Miss, Miss, Hit, Hit, Miss, Miss, Hit, Miss O d. Miss, Miss, Miss, Miss, Hit, Miss, Miss, Miss, Miss, Hit O e. Miss, Miss, Miss, Miss, Hit, Hit, Miss, Miss, Miss, Hit
- For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache.Tag Index Offset31–10 9–5 4–01. What is the cache block size (in words)?2. How many entries does the cache have?3. What is the ratio between total bits required for such a cache implementation over the data storage bits?Starting from power on, the following byte-addressed cache references are recorded. Address 0 4 16 132 232 160 1024 30 140 3100 180 2180 How many blocks are replaced? What is the hit ratio? List the fi nal state of the cache, with each valid entry represented as a record of <index, tag, data>Question 18 Suppose we have a byte-addressable computer using 2-way set associative mapping with 16-bit main memory addresses and 32 blocks of cache. Suppose also that each block contains 8 bytes. The size of the block offset field is bits, the bits. size of the set field is bits, and the size of the tag hield isGiven that a 4-way set associative cache memory has 64 KB data and each block contains 32 bytes. The main memory capacity is 4 GB. a. Find the number of bits for the main memory address. ANSWER: bits b. How many blocks are there in a set? ANSWER: blocks c. How many sets the cache has? ANSWER: d. The main memory address format is => | Tag: e. Which set will be mapped by the main memory address 458195h. ANSWER: sets bits | Set: bits | Word: bits | (in decimal)
- A two-level cache hierarchy of L1 and L2 with 2 and 3 blocks respectively is designed. Both L1 and L2 are fully-associative with LRU replacement policy. A sequence of references (block addresses from left to right, denoted as letters) is given in the table. Both caches are empty initially. You need to simulate the contents of L1 and L2 for the given sequence. Note that each request goes to L1 first. A request is issued to L2 only if it misses L1. In case of a L2 hit, the requested block is fetched from L2 and placed into L1, both in the MRU position. In case of a L2 miss, the block is loaded from memory into both L1 and L2 caches in the MRU position. The cache contents are displayed by the block addresses from MRU position to LRU position, separated by a comma.Given that a 4-way set associative cache memory has 64 KB data and each block contains 32 bytes. The main memory capacity is 4 GB. a. Find the number of bits for the main memory address. ANSWER: b. How many blocks are there in a set? ANSWER: c. How many sets the cache has? ANSWER: d. The main memory address format is => | Tag: bits | blocks sets bits | Set: e. Which set will be mapped by the main memory address 458195h. ANSWER: decimal) bits bits | Word: (inFor a direct-mapped cache design with a 32-bit address, the following bits of the address areused to access the cache.Tag Index Offset31–10 9–6 5–0a– What is the cache block size (in words)? b – How many entries does the cache have? c – What is the ratio between total bits required for such a cache implementation overthe data storage bits?
- Suppose we have a system with the following properties:The memory is byte addressable.Memory accesses are to 1-byte words (not to 4-byte words).Addresses are 13 bits wide.The cache is 4-way set associative (E = 4), with a 4-byte block size(B = 4) and eight sets (S = 8).Consider the following cache state. All addresses, tags, and valuesare given in hexadecimal format. The Index column contains the set index for each set of four lines. The Tag columns contain the tag value for each line. The V columns contain the valid bit for each line. The Bytes 0−3 columns contain the data for each line, numbered left to right starting with byte 0 on the left. A. What is the size (C) of this cache in bytes?B. The box that follows shows the format of an address (1 bit perbox). Indicate (by labeling the diagram) the fields that would beused to determine the following:CO. The cache block offsetCI. The cache set indexCT. The cache tagSuppose we have a byte-addressable computer with a cache that holds 8 blocks of 16 bytes each. Assuming that each memory address has 16 bits, to which cache block would the hexadecimal address 0x13F map if the computer uses direct mapping? Blocks are numbered starting at 0.Caches are important to providing a high-performance memory hierarchy toprocessors. Below is a list of 32-bit memory address references, given as word addresses.4, 180, 43, 2, 191, 88, 190, 14, 181, 44, 186, 253 a. For each of these references, identify the binary address, the tag, and the indexgiven a direct-mapped cache with 16 one-word blocks. Also list if each reference is a hitor a miss, assuming the cache is initially empty.b. For each of these references, identify the binary address, the tag, and the indexgiven a direct-mapped cache with two-word blocks and a total size of 8 blocks. Also listif each reference is a hit or a miss, assuming the cache is initially empty.