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Solve the following question(s) in the Questions section of your next report. 1. a) Use the full adder vhd made in lab 5 and the xogate.vhd defined below as components to design a 4-bit adder/ subtractor using structural Modeling in VHDL. Name the entity as add subtractor. The entity should have the following ports: (A, B: in atdegis vecter (3 downte 0); M: in atd legis Sout: out atdhegis; s: out atd legis vectex (3 downta 0)); Make sure to write your name as a comment at the beginning of the VHDL file. Include a screenshot of your code. b) Use EDAPlayground and the testbench code provided below to test your code. Include a screenshot of the complete timing diagram generated using EDAPlayground. The testbench should test for the cases 3+2 and 6-1. library jeee; use worki use ieee.std_logic_1164.all; entity 9ata is Bora, b: in statis; y: out stargis) 7 end 89: architecture bebax of xoRGARA is begin y < 95 bi end bebay library IEEE; use IEEE.std_logic_1164.all; entity testbench is -- empty end testbench; architecture tb of testbench is component addok Aukexacter is Dertil in strgisvestor (3 down 0); M: in stis Sout: out storais Si out stadsgivestor (3 downta 0)); end component; signal in sout: stdtraiskestak(³ downta 0); signat Gout: staraisi constant period time := 10 ns; begin DUT: addentracter port weblada Bda Kata Soutout); SRR process begin --3+2 <= "0011"; <= "0010"; M₁ <= '0'; wait for period; 6-1 < "0110"; <= "0001"; Mt <='1'; wait for period; wait for period; --Wait indefinitely. wait; end process; end;

Solve the following question(s) in the Questions section of your next report. 1. a) Use the full adder vhd made in lab 5 and the xogate.vhd defined below as components to design a 4-bit adder/ subtractor using structural Modeling in VHDL. Name the entity as add subtractor. The entity should have the following ports: (A, B: in atdegis vecter (3 downte 0); M: in atd legis Sout: out atdhegis; s: out atd legis vectex (3 downta 0)); Make sure to write your name as a comment at the beginning of the VHDL file. Include a screenshot of your code. b) Use EDAPlayground and the testbench code provided below to test your code. Include a screenshot of the complete timing diagram generated using EDAPlayground. The testbench should test for the cases 3+2 and 6-1. library jeee; use worki use ieee.std_logic_1164.all; entity 9ata is Bora, b: in statis; y: out stargis) 7 end 89: architecture bebax of xoRGARA is begin y < 95 bi end bebay library IEEE; use IEEE.std_logic_1164.all; entity testbench is -- empty end testbench; architecture tb of testbench is component addok Aukexacter is Dertil in strgisvestor (3 down 0); M: in stis Sout: out storais Si out stadsgivestor (3 downta 0)); end component; signal in sout: stdtraiskestak(³ downta 0); signat Gout: staraisi constant period time := 10 ns; begin DUT: addentracter port weblada Bda Kata Soutout); SRR process begin --3+2 <= "0011"; <= "0010"; M₁ <= '0'; wait for period; 6-1 < "0110"; <= "0001"; Mt <='1'; wait for period; wait for period; --Wait indefinitely. wait; end process; end;

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Questions: Solve the following question(s) in the Questions section of your next report. 1. a) Use the fuladder.vhd made in lab 5 and the xorgate.vhd defined below as components to design a 4-bit adder/ subtractor using structural Modeling in VHDL. Name the entity as add subtractor. The entity should have the following ports: (A, B: in stdadegis.vestes (3 dewate 0) ; M: in stddegis: Seut: out stddegis; s: out stdadegisvester (3 dewnte 0)); Make sure to write your name as a comment at the beginning of the VHDL file. Include a screenshot of your code. b) Use EDAPlayground and the testbench code provided below to test your code. Include a screenshot of the complete timing diagram generated using EDAPlayground The testbench should test for the cases 3+2 and 6-1. library jeee: use sorkall; use ieee.std_logic_1164.all; entity xorgata is Bertla, b: in stdJogis; y: out stadogÄR) ; end xegARR architecture bebax of xogatA is begin end bebay -- library IEEE; use IEEE.std_logic_1164.all; entity testbench is -- empty end testbench; architecture tb of testbench is component adderktKAster is porth R: in stddogifavester (3 dovatR 0); M: in stalagis; Geut: out stddogis; S out stdlogifanecter (3 dovatR O) ); end component; signal ain, Bda, sout: stdaiaeSEAK3 desaER 0); constant perigdi time := 10 ns; begin DUT: adderAuktraster port maplain, in, Min, StiMARARA: process begin 3+2 da = "0011"; biA <= "0010"; VdA = '0'; wait for period; 6-1 -- da = "0110"; bdA = "0001"; VdA <='1'; wait for period; wait for period; -- Wait indefinitely. wait; end process; end;
Transcribed Image Text:Questions: Solve the following question(s) in the Questions section of your next report. 1. a) Use the fuladder.vhd made in lab 5 and the xorgate.vhd defined below as components to design a 4-bit adder/ subtractor using structural Modeling in VHDL. Name the entity as add subtractor. The entity should have the following ports: (A, B: in stdadegis.vestes (3 dewate 0) ; M: in stddegis: Seut: out stddegis; s: out stdadegisvester (3 dewnte 0)); Make sure to write your name as a comment at the beginning of the VHDL file. Include a screenshot of your code. b) Use EDAPlayground and the testbench code provided below to test your code. Include a screenshot of the complete timing diagram generated using EDAPlayground The testbench should test for the cases 3+2 and 6-1. library jeee: use sorkall; use ieee.std_logic_1164.all; entity xorgata is Bertla, b: in stdJogis; y: out stadogÄR) ; end xegARR architecture bebax of xogatA is begin end bebay -- library IEEE; use IEEE.std_logic_1164.all; entity testbench is -- empty end testbench; architecture tb of testbench is component adderktKAster is porth R: in stddogifavester (3 dovatR 0); M: in stalagis; Geut: out stddogis; S out stdlogifanecter (3 dovatR O) ); end component; signal ain, Bda, sout: stdaiaeSEAK3 desaER 0); constant perigdi time := 10 ns; begin DUT: adderAuktraster port maplain, in, Min, StiMARARA: process begin 3+2 da = "0011"; biA <= "0010"; VdA = '0'; wait for period; 6-1 -- da = "0110"; bdA = "0001"; VdA <='1'; wait for period; wait for period; -- Wait indefinitely. wait; end process; end;
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