Reference to the following Figure (Figure 5.6 or your book), where you designed 1Mbytememory by applied chip group enabling on 256 Kbyte.Draw a similar 2Mbyte memory.Memoryaddressregister(MAR)AlB1ciDIMemorybufferregister(MBR)15121/512Bit 1A2B2All chips 512 words by512 bits. 2-terminal cellsA71512B7D7GroupChipgroupenableA8B8C8D8Select 1of 415121/512groupsEBit 8Figure 5.6 1-Mbyte Memory OrganizationABCA1/5 121/5121/51 2||

Actually, memory is a used to stores the data.

Reference to the following Figure (Figure 5.6 or your book), where you designed 1Mby memory by applied chip group enabling on 256 Kbyte. Draw a similar 2Mbyte memory. Memory address register (MAR) A1 B1 ci DI Memory buffer 1512 1/512 register (MBR) Bit 1 A2 B2 All chips 512 words by 512 bits. 2-termial cells A7 1512 B7 C7 D7 Group Chip group enable Select 1 A8 B8 C8 D8 of 4 1512 1/512 groups Bit 8 Figure 5.6 1-Mbyte Memory Organization 1/512 ZISA 1/51 2

Reference to the following Figure (Figure 5.6 or your book), where you designed 1Mby memory by applied chip group enabling on 256 Kbyte. Draw a similar 2Mbyte memory. Memory address register (MAR) A1 B1 ci DI Memory buffer 1512 1/512 register (MBR) Bit 1 A2 B2 All chips 512 words by 512 bits. 2-termial cells A7 1512 B7 C7 D7 Group Chip group enable Select 1 A8 B8 C8 D8 of 4 1512 1/512 groups Bit 8 Figure 5.6 1-Mbyte Memory Organization 1/512 ZISA 1/51 2

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

See similar textbooks

Similar questions

How many bits are necessary to address a 4M x16 Main Memory when it is Byte addressable?
How many memory chips of 2 K x4 bits are required to construct 1 M x8 bit memory?
A memory chip has 27 address lines, 10 data lines and 4 control lines. What is the maximum total of bits that can be stored in the chip? Present your result as a number using only digits. For example: 12345
A memory array can store 64 Tbytes. If each word in the memory is made of 8 bits, how many bits are needed in the address bus?
In a dynamic random access memory (DRAM) computer chip, each memory cell chiefly consists of a capacitor for charge storage. Each of these cells represents a single binary-bit value of 1 when its 35-fFfcapacitor (1fF=10^−15F) is charged at 1.5 V, or 0 when uncharged at 0 V. A)When it is fully charged, how many excess electrons are on a cell capacitor's negative plate? B) After charge has been placed on a cell capacitor's plate, it slowly "leaks" off (through a variety of mechanisms) at a constant rate of 0.30 fC/s. How long does it take for the potential difference across this capacitor to decrease by 1.0% from its fully charged value? (Because of this leakage effect, the charge on a DRAM capacitor is "refreshed" many times per second.) Express your answer to two significant figures and include the appropriate units.
Suppose a DRAM memory has 4 K rows in its array of bit cells, its refreshing period is 64 ms and 4 clock cycles are needed to access each row. What is the time needed to refresh the memory if clock rate is 133 MHz? What fraction of the memory's time is spent performing refreshes?
A common bus in a computer connects 16 source registers (each register is 32 bits) and one memory unit with word size of 32 bits also. If the bus is designed using multiplexers, answer the following: • What is the minimum number of multiplexers required? What is the minimum number of select lines each multiplexer has? If the bus is designed with three-state buffers and decoders, answer the following: • What is the minimum number of three-state buffers required? • What is the minimum number of decoders required? • What is the minimum size of each decode
The size of the memory could be given as: Size of the memory =Number of Words× Number of bits per word What will be the number of address lines and data lines required to construct a memory circuit of size 256 X 32 using a decoder and a multiplexer. Explanation needed. Solve if you can explain. Otherwise report. Help
How many bits are required to address a 1M × 8 main memory if Main memory is byte addressable?
Consider the following situation: In an 8088-based microprocessor, it is needed to interface with 6 LED devices with PPIs: determine the value of the control word to configure one PPI-chip? A. A2 H B. B4 H C. A4 H D. 80 H E. 9B H F. None
Suppose we have a 16KB byte-addressable memory that is 16-way low-order interleaved. What is the size of the memory address module offset field? Explain why.
How many bits are required to address a 1M × 8 main memory if Main memory is word addressable?