Ql: Assume we have a CP register is 16 bits length and the Register File has two read ports and one write port. (a) Draw the structure of the Register file. (b) Determine the width in bits of the read and write ports. (c) Determine the width in bits of the RS1, RS2, and RD inputs. Register File that consists of two registers, each

Ql: Assume we have a CP register is 16 bits length and the Register File has two read ports and one write port. (a) Draw the structure of the Register file. (b) Determine the width in bits of the read and write ports. (c) Determine the width in bits of the RS1, RS2, and RD inputs. Register File that consists of two registers, each

Name: Ql: Assume we have a CPU Register File that consists of two registers
Uploaded: 2024-03-20T06:51:23.000Z
Channel: Bartleby
Description: Ql: Assume we have a CPU Register File that consists of two registers, eachregister is 16 bits length and the Register File has two read ports and one writeport.(a) Draw the structure of the Register file.(b) Determine the width in bits of the read

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter2: Introduction To Systems Architecture

Section: Chapter Questions

Problem 2VE: A(n) __________ is a storage location implemented in the CPU.

See similar textbooks

Similar questions

The code segment, the data segment, and the stack segment are all distinct. Then, determine the mix of registers utilized to address data objects in each segment.
Microprocessor assembly code: There are 25 1-band numbers stored in memory starting from 1000H address. Write the program that shows the numbers greater than 50 with LEDs connected to port 2 with 2s intervals Tips: If the numbers are 01-03-55-21-51-34 ...... 66-FF 55-51 -..... 66-FF will be sent to Port 2 at 2s intervals. It should be assumed that the numbers were pre-entered into memory with the C 1000 command.
Difference between address bus & data bus is: a) Both carry bits in either directions. b) Address bus is only for addressing signals. c) Data wires are only for data signals. d) Address bus is bidirectional while data bus Is unidirectional e) None of the options here.
Translate the following C code to MIPS. Assume that the variables i and j are assigned to registers $s0 and $s1, respectively. Assume that the base address of the arrays A and B are in registers $s6 and $s7, respectively. Assume that the elements of the arrays A and B are 4-byte words. If you need to use registers $t0 through $t9 or $s0 through $s7, use the lower-numbered registers first. where (i < j ){ B[ i ] = A [ i + 1 ] + A [ i ]; i++; }
Computer Science A computer uses a memory of 64K words with 16 bits in each word.It has the following registers: PC, AR, TR, AC, DR and IRA memory-reference instruction consists of two words: an 16-bit operation-code(one word) and an address field (in the next word).a-List the sequence of microoperations for fetching a memory reference instructionand then placing the operand in DR. Start from timing signal To.b-Design the logic control gates arrangement to perform the fetch instructions.
The memory unit of a computer has 256K words of 32 bits each. The computer has an instruction format with 4 fields: an opcode field; a mode field to specify 1 of 7 addressing modes; a register address field to specify one of 60 registers; and a memory address field. Assume an instruction is 32 bits long. Answer the following:a. How large must the mode field be?b. How large must the register field be?c. How large must the address field be?d. How large is the opcode field?
16. A pipelined datapath must have separate instruction and data memories because the format of instructions is different from the format of data. A. True B. False PART B 17. What is the single-precision floating-point format of the decimal number 25600? A. 0110 0110 1100 1000 0000 0000 0000 0000 B. 0100 0110 1100 1000 0000 0000 0000 0000 C. 0100 0110 1100 1100 0000 0000 0000 0000 D. 0100 1110 1100 1000 0000 0000 0000 0000 18. What does the following single-precision floating-point number represent? 01000011101100000010000000000000 A. (352.25)1o B. (35.225)10 C. (523.25)10 D. None of the above 19. Consider the floating-point 4-digit numbers showing below: 1.010 x 2-1 and 1.011 x 2-3. Using floating-point addition procedure, the result of adding these two numbers will be: A. 1.110 X 2 B. 1.011 X 2 C. 1.100 X 2! D. None of the above. 20. One of the MIPS advantages is that it uses the same registers for integer and floating-point numbers. A. True B. False 21. means if a program references…
For the RISC-V assembly instructions below, what is the corresponding C statement? Assume that the variables f, g, h, i, and 3 are assigned to registers x5, x6, x7, x28, and x29, respectively. Assume that the base address of the arrays A and B are in registers x10 and 11, respectively. sub x30, x28, x29 slli x30, x30, 2 add x3, x30, x10 add x4, x30, x11 Iw x30, 0(x3) 1w x31, 0(x4) add x30, x30, x31 sw x30, 16 (x11)
For the RISC-V assembly instructions below, what is the corresponding C statement? Assume that the variables f, g, h, i, and j are assigned to registers x5, x6, x7, x28, and x29, respectively. Assume that the base address of the arrays A and B are in registers x10 and x11, respectively: sub x30, x28, x29 slli x30, x30, 2 add x3, x30, x10 add x4, x30, x11 lw x30, 0 (x3) 1w x31, 0 (x4) add x30, x30, x31 sw x30, 16 (x11)
A set of ten packed BCD numbers is stored in the memory location starting at 3050H. i. Write a program with a subroutine to add these numbers in BCD. If a carry is generated, save it in register B, and adjust it for BCD. The final sum will be less than 9999sCD. ii. Write a second subroutine to unpack the BCD sum stored in registers A and B, and store them in the memory locations starting at 3070H. The most significant digit (BCD4) should be stored at 3070H and the least significant digit (BCD) at 3073H.
QuedT: Choose the correct answer: [ Opcode, funct3 and funct7/6 in instruction format are used to identify the: (a) function. (b) instruction. (e) branch. (d) memory address. The register that hold the address of the current instruction being executed is called: (a) saved register. (b) global pointer. (e) stack pointer. (d) program counter. Placing the executable file into the memory for execution by the processor is the role of (a) assembler. (b) linker. (e) loader. (d) compiler. The part which responsible for transmitting the data to/from the processor is: (a) control unit. (b) Datapath. (c) data bus. (d) memory. Parallel hardware cannot be used for faster division because: (a) subtraction is conditional on sign of remainder. (b) multiplication is conditional on sign of remainder. (c) subtraction is conditional on sign of divisor. (d) multiplication is conditional on sign of divisor. we cannot slower the clock cycle to fit the floating-point adder algorithm into one clock cycle…
26. Find the time delay in the following program if the crystal frequency is 1 MHz. Do not ignore the time delay due to the first and last instruction. DELAY: LDI R16, 30 AGAIN: LDI R17, 35 HERE: NOP NOP DEC R17 BRNE HERE DEC R16 BRNE AGAIN RET