Problem 1 SP11.1 (Dr. Underwood, Dr. Fish, Dr. Graybill) The 7485 IC is a 4-bit digital comparator and has a Multisim pin-out diagram as shown below. (The numbers shown on the pins around the outside of the symbol are the pin numbers.) For the given input binary data sequence below, draw the timing diagram you expect to see for the output waveforms OAGTB (A > B), OAEQB (A = B) and OALTB (A B) are active-high enable pins, which means that they must be pulled high (connected to Vcc) in order for the outputs OAGTB, OAEQB, and OALTB to function. You can assume that pins 2, 3, and 4 have been properly pulled high.
Problem 1 SP11.1 (Dr. Underwood, Dr. Fish, Dr. Graybill) The 7485 IC is a 4-bit digital comparator and has a Multisim pin-out diagram as shown below. (The numbers shown on the pins around the outside of the symbol are the pin numbers.) For the given input binary data sequence below, draw the timing diagram you expect to see for the output waveforms OAGTB (A > B), OAEQB (A = B) and OALTB (A B) are active-high enable pins, which means that they must be pulled high (connected to Vcc) in order for the outputs OAGTB, OAEQB, and OALTB to function. You can assume that pins 2, 3, and 4 have been properly pulled high.
Chapter22: Sequence Control
Section: Chapter Questions
Problem 6SQ: Draw a symbol for a solid-state logic element AND.
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