Problem 1 SP11.1 (Dr. Underwood, Dr. Fish, Dr. Graybill) The 7485 IC is a 4-bit digital comparator and has a Multisim pin-out diagram as shown below. (The numbers shown on the pins around the outside of the symbol are the pin numbers.) For the given input binary data sequence below, draw the timing diagram you expect to see for the output waveforms OAGTB (A > B), OAEQB (A = B) and OALTB (A B) are active-high enable pins, which means that they must be pulled high (connected to Vcc) in order for the outputs OAGTB, OAEQB, and OALTB to function. You can assume that pins 2, 3, and 4 have been properly pulled high.

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Chapter22: Sequence Control
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Problem 6SQ: Draw a symbol for a solid-state logic element AND.
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Problem 1
SP11.1 (Dr. Underwood, Dr. Fish, Dr. Graybill)
The 7485 IC is a 4-bit digital comparator and has a Multisim pin-out diagram as shown below. (The
numbers shown on the pins around the outside of the symbol are the pin numbers.) For the given input
binary data sequence below, draw the timing diagram you expect to see for the output waveforms
OAGTB (A > B), OAEQB (A = B) and OALTB (A <B) in the bottom three rows. A3 and B3 are the most-
significant bits.
Note: Pins 2 (ALTB, A <B), 3 (AEQB, A = B), and 4 AGTB (A > B) are active-high enable pins, which means
that they must be pulled high (connected to Vcc) in order for the outputs OAGTB, OAEQB, and OALTB to
function. You can assume that pins 2, 3, and 4 have been properly pulled high.
A3
A2
A1
AO
B3
B2
B1
BO
A>B
A=B
A<B
0 0 0 0
0 0 0 0
1
0
0
OLOO
0
1
0
0
1
1
1
1
1
1
---
1
1
1
1
1
0
0
0
1
O
LLOO
1
1
0
OOHL
0
0
1
1
0
1
0
1
1
оонн
OLOO
0
1
0
OOOO
0
0
0
0
VCC
15
1
13
14
12
11
10
9
4
3
2
A3
B3
A2
ABAB
NN WW
B2
A1
B1
ama m
OOTT
AO
ВО
AGTB
AEQB
ALTB
OAGTB
OAEQB
OALTB
7485N
5
6
7
Transcribed Image Text:Problem 1 SP11.1 (Dr. Underwood, Dr. Fish, Dr. Graybill) The 7485 IC is a 4-bit digital comparator and has a Multisim pin-out diagram as shown below. (The numbers shown on the pins around the outside of the symbol are the pin numbers.) For the given input binary data sequence below, draw the timing diagram you expect to see for the output waveforms OAGTB (A > B), OAEQB (A = B) and OALTB (A <B) in the bottom three rows. A3 and B3 are the most- significant bits. Note: Pins 2 (ALTB, A <B), 3 (AEQB, A = B), and 4 AGTB (A > B) are active-high enable pins, which means that they must be pulled high (connected to Vcc) in order for the outputs OAGTB, OAEQB, and OALTB to function. You can assume that pins 2, 3, and 4 have been properly pulled high. A3 A2 A1 AO B3 B2 B1 BO A>B A=B A<B 0 0 0 0 0 0 0 0 1 0 0 OLOO 0 1 0 0 1 1 1 1 1 1 --- 1 1 1 1 1 0 0 0 1 O LLOO 1 1 0 OOHL 0 0 1 1 0 1 0 1 1 оонн OLOO 0 1 0 OOOO 0 0 0 0 VCC 15 1 13 14 12 11 10 9 4 3 2 A3 B3 A2 ABAB NN WW B2 A1 B1 ama m OOTT AO ВО AGTB AEQB ALTB OAGTB OAEQB OALTB 7485N 5 6 7
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